SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1326 | 1326 | 0 | 0 |
OutputsKnown_A | 349221090 | 349001766 | 0 | 0 |
gen_flops.OutputDelay_A | 174610545 | 174495852 | 0 | 1989 |
gen_no_flops.OutputDelay_A | 174610545 | 174500883 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1326 | 1326 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T35 | 6 | 6 | 0 | 0 |
T40 | 6 | 6 | 0 | 0 |
T41 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 349221090 | 349001766 | 0 | 0 |
T1 | 5228766 | 5228460 | 0 | 0 |
T2 | 189540 | 189084 | 0 | 0 |
T3 | 246318 | 244734 | 0 | 0 |
T4 | 354510 | 352650 | 0 | 0 |
T5 | 683850 | 681846 | 0 | 0 |
T7 | 107604 | 107070 | 0 | 0 |
T8 | 12510 | 12066 | 0 | 0 |
T35 | 16932 | 16530 | 0 | 0 |
T40 | 122064 | 121644 | 0 | 0 |
T41 | 1712730 | 1712376 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174610545 | 174495852 | 0 | 1989 |
T1 | 2614383 | 2614221 | 0 | 9 |
T2 | 94770 | 94533 | 0 | 9 |
T3 | 123159 | 122331 | 0 | 9 |
T4 | 177255 | 176280 | 0 | 9 |
T5 | 341925 | 340878 | 0 | 9 |
T7 | 53802 | 53526 | 0 | 9 |
T8 | 6255 | 6024 | 0 | 9 |
T35 | 8466 | 8256 | 0 | 9 |
T40 | 61032 | 60813 | 0 | 9 |
T41 | 856365 | 856179 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174610545 | 174500883 | 0 | 0 |
T1 | 2614383 | 2614230 | 0 | 0 |
T2 | 94770 | 94542 | 0 | 0 |
T3 | 123159 | 122367 | 0 | 0 |
T4 | 177255 | 176325 | 0 | 0 |
T5 | 341925 | 340923 | 0 | 0 |
T7 | 53802 | 53535 | 0 | 0 |
T8 | 6255 | 6033 | 0 | 0 |
T35 | 8466 | 8265 | 0 | 0 |
T40 | 61032 | 60822 | 0 | 0 |
T41 | 856365 | 856188 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 221 | 221 | 0 | 0 |
OutputsKnown_A | 58203515 | 58166961 | 0 | 0 |
gen_flops.OutputDelay_A | 58203515 | 58165284 | 0 | 663 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221 | 221 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58165284 | 0 | 663 |
T1 | 871461 | 871407 | 0 | 3 |
T2 | 31590 | 31511 | 0 | 3 |
T3 | 41053 | 40777 | 0 | 3 |
T4 | 59085 | 58760 | 0 | 3 |
T5 | 113975 | 113626 | 0 | 3 |
T7 | 17934 | 17842 | 0 | 3 |
T8 | 2085 | 2008 | 0 | 3 |
T35 | 2822 | 2752 | 0 | 3 |
T40 | 20344 | 20271 | 0 | 3 |
T41 | 285455 | 285393 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 221 | 221 | 0 | 0 |
OutputsKnown_A | 58203515 | 58166961 | 0 | 0 |
gen_flops.OutputDelay_A | 58203515 | 58165284 | 0 | 663 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221 | 221 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58165284 | 0 | 663 |
T1 | 871461 | 871407 | 0 | 3 |
T2 | 31590 | 31511 | 0 | 3 |
T3 | 41053 | 40777 | 0 | 3 |
T4 | 59085 | 58760 | 0 | 3 |
T5 | 113975 | 113626 | 0 | 3 |
T7 | 17934 | 17842 | 0 | 3 |
T8 | 2085 | 2008 | 0 | 3 |
T35 | 2822 | 2752 | 0 | 3 |
T40 | 20344 | 20271 | 0 | 3 |
T41 | 285455 | 285393 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 221 | 221 | 0 | 0 |
OutputsKnown_A | 58203515 | 58166961 | 0 | 0 |
gen_no_flops.OutputDelay_A | 58203515 | 58166961 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221 | 221 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 221 | 221 | 0 | 0 |
OutputsKnown_A | 58203515 | 58166961 | 0 | 0 |
gen_flops.OutputDelay_A | 58203515 | 58165284 | 0 | 663 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221 | 221 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58165284 | 0 | 663 |
T1 | 871461 | 871407 | 0 | 3 |
T2 | 31590 | 31511 | 0 | 3 |
T3 | 41053 | 40777 | 0 | 3 |
T4 | 59085 | 58760 | 0 | 3 |
T5 | 113975 | 113626 | 0 | 3 |
T7 | 17934 | 17842 | 0 | 3 |
T8 | 2085 | 2008 | 0 | 3 |
T35 | 2822 | 2752 | 0 | 3 |
T40 | 20344 | 20271 | 0 | 3 |
T41 | 285455 | 285393 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 221 | 221 | 0 | 0 |
OutputsKnown_A | 58203515 | 58166961 | 0 | 0 |
gen_no_flops.OutputDelay_A | 58203515 | 58166961 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221 | 221 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 221 | 221 | 0 | 0 |
OutputsKnown_A | 58203515 | 58166961 | 0 | 0 |
gen_no_flops.OutputDelay_A | 58203515 | 58166961 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221 | 221 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T40 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 58203515 | 58166961 | 0 | 0 |
T1 | 871461 | 871410 | 0 | 0 |
T2 | 31590 | 31514 | 0 | 0 |
T3 | 41053 | 40789 | 0 | 0 |
T4 | 59085 | 58775 | 0 | 0 |
T5 | 113975 | 113641 | 0 | 0 |
T7 | 17934 | 17845 | 0 | 0 |
T8 | 2085 | 2011 | 0 | 0 |
T35 | 2822 | 2755 | 0 | 0 |
T40 | 20344 | 20274 | 0 | 0 |
T41 | 285455 | 285396 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |