Line Coverage for Module :
tlul_rsp_intg_chk
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 23 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 50 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
23 |
1 |
1 |
47 |
1 |
1 |
50 |
1 |
1 |
Cond Coverage for Module :
tlul_rsp_intg_chk
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 47
EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
------1----- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T8,T16 |
1 | 0 | Covered | T2,T16,T17 |
1 | 1 | Covered | T16,T27,T28 |
LINE 47
SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T27,T28,T31 |
1 | 0 | Covered | T16,T27,T31 |
Assert Coverage for Module :
tlul_rsp_intg_chk
Assertion Details
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
438 |
438 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |