Module Definition
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Module : tlul_adapter_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.tl_adapter_host_sba 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.tl_adapter_host_sba

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.14 100.00 100.00 75.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 100.00 100.00 100.00
u_rsp_chk 93.93 100.00 100.00 75.71 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_host
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS13244100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 1 1
MISSING_ELSE
141 1 1
145 1 1
149 1 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable


Cond Coverage for Module : tlul_adapter_host
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT2,T16,T17
1CoveredT1,T2,T3

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT2,T16,T17
1CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT2,T16,T17
1CoveredT2,T16,T17

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT2,T3,T8
01CoveredT16,T28,T31
10CoveredT1,T2,T3

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T27,T28
10CoveredT16,T27,T28

Branch Coverage for Module : tlul_adapter_host
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 94 2 2 100.00
IF 132 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 94 ((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T16,T17


LineNo. Expression -1-: 132 if ((!rst_ni)) -2-: 134 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T16,T27,T28
0 0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_host
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 158363891 12166 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 158363891 12166 0 0
T2 258100 24 0 0
T3 1753 0 0 0
T4 248495 0 0 0
T7 34620 0 0 0
T8 14261 0 0 0
T9 764079 0 0 0
T16 92354 8 0 0
T17 148968 106 0 0
T27 0 10 0 0
T28 0 966 0 0
T45 297441 14 0 0
T46 2982 0 0 0
T47 0 79 0 0
T48 0 44 0 0
T57 0 45 0 0
T66 0 33 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%