Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 277964 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 667789 1 T1 2 T2 1 T3 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 517047 1 T2 1 T4 7 T5 13
values[0x0] 183543 1 T1 7 T3 2 T4 8
values[0x1] 245163 1 T1 6 T2 1 T3 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 184323 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 761430 1 T1 4 T2 1 T3 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4208 1 T6 1 T34 1 T58 5
valid_sources[0x01] 3746 1 T146 1 T63 6 T61 1
valid_sources[0x02] 3155 1 T141 1 T35 4 T58 4
valid_sources[0x03] 3494 1 T134 1 T16 2 T165 2
valid_sources[0x04] 3403 1 T129 1 T165 1 T63 5
valid_sources[0x05] 3672 1 T31 1 T150 1 T141 1
valid_sources[0x06] 4123 1 T16 1 T58 7 T63 5
valid_sources[0x07] 3509 1 T141 2 T58 6 T63 6
valid_sources[0x08] 3502 1 T38 11 T141 1 T63 4
valid_sources[0x09] 3537 1 T54 2 T134 2 T141 1
valid_sources[0x0a] 3853 1 T63 4 T61 2 T64 22
valid_sources[0x0b] 3205 1 T7 2 T58 2 T63 2
valid_sources[0x0c] 4105 1 T39 1 T58 4 T63 7
valid_sources[0x0d] 3578 1 T17 1 T141 1 T16 1
valid_sources[0x0e] 3562 1 T4 2 T31 2 T150 1
valid_sources[0x0f] 3391 1 T57 2 T129 1 T166 1
valid_sources[0x10] 3873 1 T4 1 T57 1 T16 2
valid_sources[0x11] 3679 1 T129 1 T58 5 T63 3
valid_sources[0x12] 3645 1 T54 3 T57 2 T150 1
valid_sources[0x13] 3622 1 T3 1 T31 2 T17 1
valid_sources[0x14] 3506 1 T58 8 T63 5 T64 23
valid_sources[0x15] 3254 1 T31 1 T166 3 T58 6
valid_sources[0x16] 4048 1 T2 1 T54 1 T58 1
valid_sources[0x17] 3342 1 T167 2 T166 2 T58 2
valid_sources[0x18] 3290 1 T58 3 T63 7 T64 11
valid_sources[0x19] 3501 1 T4 1 T44 1 T137 11
valid_sources[0x1a] 4194 1 T34 1 T58 3 T63 5
valid_sources[0x1b] 3658 1 T148 1 T16 1 T58 7
valid_sources[0x1c] 3592 1 T57 1 T129 1 T58 2
valid_sources[0x1d] 3603 1 T4 1 T57 1 T150 1
valid_sources[0x1e] 4277 1 T31 1 T54 2 T168 1
valid_sources[0x1f] 3873 1 T165 2 T19 1 T58 5
valid_sources[0x20] 4152 1 T44 1 T150 1 T58 2
valid_sources[0x21] 3287 1 T141 1 T58 2 T63 4
valid_sources[0x22] 3504 1 T14 3 T6 2 T165 1
valid_sources[0x23] 3911 1 T134 1 T141 2 T58 3
valid_sources[0x24] 4077 1 T131 1 T141 1 T39 1
valid_sources[0x25] 4101 1 T31 1 T129 1 T141 2
valid_sources[0x26] 3658 1 T54 2 T34 2 T166 6
valid_sources[0x27] 3909 1 T129 1 T165 3 T169 1
valid_sources[0x28] 3780 1 T57 2 T134 1 T165 1
valid_sources[0x29] 3623 1 T2 1 T129 4 T169 1
valid_sources[0x2a] 3609 1 T146 2 T40 4 T58 1
valid_sources[0x2b] 4213 1 T31 1 T16 1 T58 6
valid_sources[0x2c] 3374 1 T17 1 T150 1 T165 1
valid_sources[0x2d] 4507 1 T57 1 T129 1 T16 1
valid_sources[0x2e] 3182 1 T58 2 T63 5 T64 12
valid_sources[0x2f] 4888 1 T134 1 T137 2 T22 1
valid_sources[0x30] 3283 1 T16 1 T169 1 T58 4
valid_sources[0x31] 3802 1 T4 1 T14 1 T129 1
valid_sources[0x32] 3722 1 T141 2 T170 2 T58 3
valid_sources[0x33] 3381 1 T150 1 T58 7 T61 1
valid_sources[0x34] 4957 1 T129 1 T19 1 T58 2
valid_sources[0x35] 3476 1 T17 1 T129 1 T171 3
valid_sources[0x36] 3342 1 T58 1 T63 9 T64 23
valid_sources[0x37] 4024 1 T150 2 T58 2 T63 3
valid_sources[0x38] 3869 1 T165 1 T167 3 T170 1
valid_sources[0x39] 3639 1 T44 1 T141 4 T169 1
valid_sources[0x3a] 3543 1 T134 1 T58 6 T63 2
valid_sources[0x3b] 3926 1 T37 5 T58 1 T63 3
valid_sources[0x3c] 3475 1 T129 2 T16 1 T165 1
valid_sources[0x3d] 3712 1 T58 2 T63 2 T64 26
valid_sources[0x3e] 3863 1 T41 9 T7 2 T58 8
valid_sources[0x3f] 3426 1 T44 1 T15 13 T141 2
valid_sources[0x40] 3659 1 T141 1 T58 8 T63 4
valid_sources[0x41] 3508 1 T54 4 T141 2 T172 3
valid_sources[0x42] 3760 1 T39 2 T170 1 T63 3
valid_sources[0x43] 3464 1 T63 4 T61 1 T64 28
valid_sources[0x44] 4027 1 T16 1 T165 1 T58 3
valid_sources[0x45] 3603 1 T58 9 T63 4 T61 2
valid_sources[0x46] 3525 1 T141 1 T58 1 T63 1
valid_sources[0x47] 3432 1 T34 1 T58 7 T63 6
valid_sources[0x48] 3309 1 T58 1 T63 5 T64 12
valid_sources[0x49] 3523 1 T54 2 T19 1 T58 2
valid_sources[0x4a] 3568 1 T134 1 T150 1 T141 1
valid_sources[0x4b] 3498 1 T37 4 T34 2 T58 2
valid_sources[0x4c] 3536 1 T31 1 T58 4 T63 5
valid_sources[0x4d] 3260 1 T57 2 T19 1 T58 2
valid_sources[0x4e] 3831 1 T141 1 T58 1 T63 4
valid_sources[0x4f] 3235 1 T141 1 T58 2 T63 5
valid_sources[0x50] 3364 1 T37 1 T141 1 T58 4
valid_sources[0x51] 3276 1 T58 1 T63 3 T61 1
valid_sources[0x52] 3408 1 T58 2 T63 6 T64 7
valid_sources[0x53] 3378 1 T44 1 T141 1 T16 1
valid_sources[0x54] 5236 1 T134 1 T16 1 T34 1
valid_sources[0x55] 4039 1 T129 3 T6 2 T58 2
valid_sources[0x56] 3296 1 T1 2 T54 1 T6 1
valid_sources[0x57] 4426 1 T169 2 T58 3 T63 2
valid_sources[0x58] 3355 1 T4 2 T150 1 T141 1
valid_sources[0x59] 3465 1 T57 1 T150 1 T173 1
valid_sources[0x5a] 3724 1 T58 1 T63 7 T64 20
valid_sources[0x5b] 4100 1 T54 1 T44 1 T141 1
valid_sources[0x5c] 3487 1 T174 2 T171 1 T166 6
valid_sources[0x5d] 4053 1 T44 1 T129 1 T34 1
valid_sources[0x5e] 3874 1 T54 1 T16 2 T63 4
valid_sources[0x5f] 3283 1 T57 1 T168 1 T165 2
valid_sources[0x60] 4272 1 T4 1 T34 1 T58 4
valid_sources[0x61] 3354 1 T34 1 T171 2 T170 2
valid_sources[0x62] 3870 1 T57 2 T63 6 T64 21
valid_sources[0x63] 3510 1 T31 2 T16 2 T34 1
valid_sources[0x64] 3603 1 T26 15 T141 1 T170 1
valid_sources[0x65] 3491 1 T54 2 T129 1 T58 2
valid_sources[0x66] 3099 1 T22 1 T58 3 T63 3
valid_sources[0x67] 3414 1 T129 3 T58 6 T63 6
valid_sources[0x68] 3534 1 T31 1 T34 3 T58 3
valid_sources[0x69] 3467 1 T16 1 T34 1 T22 1
valid_sources[0x6a] 4237 1 T14 4 T63 8 T64 8
valid_sources[0x6b] 3379 1 T129 2 T150 1 T58 1
valid_sources[0x6c] 3365 1 T129 1 T141 2 T34 4
valid_sources[0x6d] 3693 1 T148 1 T19 1 T58 4
valid_sources[0x6e] 4216 1 T4 1 T17 1 T58 2
valid_sources[0x6f] 5140 1 T141 1 T58 4 T63 5
valid_sources[0x70] 3480 1 T58 1 T63 9 T64 20
valid_sources[0x71] 3993 1 T150 2 T141 1 T58 5
valid_sources[0x72] 3832 1 T20 3 T52 15 T169 1
valid_sources[0x73] 3866 1 T58 1 T63 1 T61 1
valid_sources[0x74] 3454 1 T152 8 T165 1 T58 2
valid_sources[0x75] 3688 1 T170 1 T58 1 T63 6
valid_sources[0x76] 3540 1 T31 1 T54 1 T34 2
valid_sources[0x77] 3370 1 T54 1 T6 2 T58 8
valid_sources[0x78] 3122 1 T17 1 T150 1 T58 8
valid_sources[0x79] 3691 1 T31 2 T37 1 T34 2
valid_sources[0x7a] 3808 1 T58 8 T63 2 T61 1
valid_sources[0x7b] 3382 1 T44 1 T134 1 T58 1
valid_sources[0x7c] 3829 1 T166 2 T58 1 T63 3
valid_sources[0x7d] 3224 1 T165 3 T19 1 T58 6
valid_sources[0x7e] 3433 1 T1 1 T63 2 T61 4
valid_sources[0x7f] 3716 1 T129 1 T141 1 T58 5
valid_sources[0x80] 3167 1 T54 1 T16 1 T6 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 316903 1 T4 5 T5 7 T26 1
values[0x0] all_enables biggest_size 175527 1 T1 1 T3 1 T4 4
values[0x1] all_enables biggest_size 175359 1 T1 1 T2 1 T4 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 9094 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 115918 1 T1 7 T2 1 T3 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 35210 1 T58 19 T63 6 T61 66
values[0x0] 43655 1 T1 2 T2 1 T3 4
values[0x1] 46147 1 T1 5 T4 2 T36 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5828 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 119184 1 T1 7 T2 1 T3 4



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 705 1 T175 2 T176 1 T59 4
valid_sources[0x01] 343 1 T177 1 T178 1 T179 1
valid_sources[0x02] 787 1 T1 1 T128 1 T69 1
valid_sources[0x03] 612 1 T54 8 T55 1 T70 7
valid_sources[0x04] 307 1 T130 7 T61 1 T87 6
valid_sources[0x05] 327 1 T180 1 T58 1 T95 1
valid_sources[0x06] 391 1 T61 1 T62 1 T90 1
valid_sources[0x07] 695 1 T132 1 T61 1 T62 1
valid_sources[0x08] 467 1 T181 1 T182 2 T61 1
valid_sources[0x09] 420 1 T62 1 T90 2 T87 3
valid_sources[0x0a] 298 1 T183 1 T184 1 T62 1
valid_sources[0x0b] 302 1 T61 2 T62 2 T76 35
valid_sources[0x0c] 592 1 T46 1 T61 1 T82 4
valid_sources[0x0d] 391 1 T184 1 T179 1 T90 32
valid_sources[0x0e] 391 1 T5 1 T61 2 T90 1
valid_sources[0x0f] 362 1 T185 1 T142 1 T58 2
valid_sources[0x10] 325 1 T186 1 T152 9 T64 2
valid_sources[0x11] 563 1 T31 1 T22 1 T61 3
valid_sources[0x12] 332 1 T141 1 T182 2 T187 1
valid_sources[0x13] 482 1 T147 2 T188 2 T182 1
valid_sources[0x14] 404 1 T128 2 T189 3 T61 3
valid_sources[0x15] 297 1 T46 1 T75 5 T58 1
valid_sources[0x16] 581 1 T28 1 T190 1 T191 1
valid_sources[0x17] 761 1 T46 1 T69 1 T61 1
valid_sources[0x18] 891 1 T192 9 T191 1 T58 1
valid_sources[0x19] 484 1 T193 1 T167 1 T194 1
valid_sources[0x1a] 445 1 T186 3 T134 2 T62 1
valid_sources[0x1b] 349 1 T58 1 T61 1 T62 1
valid_sources[0x1c] 498 1 T195 2 T189 3 T196 1
valid_sources[0x1d] 456 1 T148 1 T197 1 T198 1
valid_sources[0x1e] 401 1 T199 2 T61 1 T64 1
valid_sources[0x1f] 359 1 T132 1 T200 1 T145 2
valid_sources[0x20] 325 1 T201 5 T138 1 T61 3
valid_sources[0x21] 458 1 T202 1 T203 1 T90 1
valid_sources[0x22] 314 1 T204 1 T205 1 T206 1
valid_sources[0x23] 403 1 T207 1 T208 1 T61 2
valid_sources[0x24] 767 1 T1 1 T207 1 T205 1
valid_sources[0x25] 590 1 T175 5 T209 13 T210 1
valid_sources[0x26] 348 1 T122 2 T28 1 T211 8
valid_sources[0x27] 355 1 T204 1 T206 7 T61 2
valid_sources[0x28] 309 1 T74 1 T212 2 T213 1
valid_sources[0x29] 423 1 T214 11 T203 1 T61 2
valid_sources[0x2a] 680 1 T5 1 T215 1 T216 1
valid_sources[0x2b] 621 1 T131 7 T186 1 T205 2
valid_sources[0x2c] 330 1 T208 1 T217 1 T61 3
valid_sources[0x2d] 548 1 T31 1 T71 2 T177 1
valid_sources[0x2e] 577 1 T28 1 T207 1 T208 1
valid_sources[0x2f] 516 1 T218 1 T61 1 T90 1
valid_sources[0x30] 486 1 T22 1 T143 1 T62 4
valid_sources[0x31] 602 1 T219 8 T95 1 T153 3
valid_sources[0x32] 293 1 T32 1 T182 1 T61 2
valid_sources[0x33] 596 1 T220 1 T173 1 T41 1
valid_sources[0x34] 887 1 T205 1 T210 1 T9 5
valid_sources[0x35] 675 1 T14 1 T151 1 T61 2
valid_sources[0x36] 976 1 T146 1 T13 4 T62 1
valid_sources[0x37] 1128 1 T221 1 T174 1 T61 1
valid_sources[0x38] 600 1 T24 1 T204 1 T165 1
valid_sources[0x39] 391 1 T207 1 T140 7 T61 1
valid_sources[0x3a] 385 1 T46 1 T137 6 T179 1
valid_sources[0x3b] 463 1 T2 1 T187 1 T222 13
valid_sources[0x3c] 354 1 T57 3 T71 1 T207 1
valid_sources[0x3d] 400 1 T223 1 T22 1 T224 1
valid_sources[0x3e] 503 1 T61 1 T90 3 T86 1
valid_sources[0x3f] 441 1 T225 17 T178 2 T61 1
valid_sources[0x40] 590 1 T128 1 T15 1 T210 1
valid_sources[0x41] 599 1 T207 1 T226 4 T82 1
valid_sources[0x42] 371 1 T1 1 T227 1 T147 2
valid_sources[0x43] 673 1 T184 2 T58 2 T64 2
valid_sources[0x44] 435 1 T46 1 T62 1 T59 3
valid_sources[0x45] 374 1 T200 1 T64 4 T62 1
valid_sources[0x46] 395 1 T228 1 T229 1 T218 1
valid_sources[0x47] 672 1 T26 5 T15 1 T186 1
valid_sources[0x48] 497 1 T134 2 T184 1 T62 2
valid_sources[0x49] 518 1 T179 1 T62 1 T85 2
valid_sources[0x4a] 431 1 T230 1 T141 1 T58 1
valid_sources[0x4b] 384 1 T141 1 T16 1 T184 1
valid_sources[0x4c] 410 1 T68 1 T193 1 T199 1
valid_sources[0x4d] 523 1 T14 1 T18 1 T61 4
valid_sources[0x4e] 298 1 T231 1 T61 2 T62 4
valid_sources[0x4f] 498 1 T175 1 T224 2 T62 1
valid_sources[0x50] 494 1 T199 1 T62 1 T82 4
valid_sources[0x51] 567 1 T58 1 T62 6 T86 2
valid_sources[0x52] 414 1 T232 1 T58 1 T64 1
valid_sources[0x53] 778 1 T71 1 T144 1 T233 4
valid_sources[0x54] 378 1 T200 1 T62 3 T82 1
valid_sources[0x55] 573 1 T234 1 T235 1 T61 1
valid_sources[0x56] 437 1 T65 1 T236 1 T61 1
valid_sources[0x57] 1185 1 T237 2 T238 9 T62 1
valid_sources[0x58] 512 1 T4 2 T5 1 T129 3
valid_sources[0x59] 589 1 T17 1 T61 1 T86 1
valid_sources[0x5a] 361 1 T8 1 T61 1 T90 1
valid_sources[0x5b] 432 1 T28 1 T239 1 T240 3
valid_sources[0x5c] 348 1 T5 1 T241 1 T148 1
valid_sources[0x5d] 461 1 T46 1 T15 1 T63 1
valid_sources[0x5e] 534 1 T169 2 T58 1 T62 2
valid_sources[0x5f] 567 1 T55 1 T61 1 T64 1
valid_sources[0x60] 708 1 T76 20 T242 2 T153 5
valid_sources[0x61] 332 1 T243 1 T178 1 T61 1
valid_sources[0x62] 475 1 T61 2 T62 2 T76 9
valid_sources[0x63] 340 1 T205 1 T58 1 T62 1
valid_sources[0x64] 365 1 T232 1 T61 1 T60 1
valid_sources[0x65] 499 1 T5 1 T58 1 T61 2
valid_sources[0x66] 539 1 T204 1 T184 1 T62 2
valid_sources[0x67] 486 1 T36 3 T128 2 T69 1
valid_sources[0x68] 433 1 T197 1 T61 1 T90 1
valid_sources[0x69] 359 1 T61 4 T64 2 T62 2
valid_sources[0x6a] 578 1 T177 1 T141 1 T206 3
valid_sources[0x6b] 508 1 T178 1 T7 1 T169 3
valid_sources[0x6c] 476 1 T138 2 T216 1 T58 1
valid_sources[0x6d] 368 1 T199 1 T62 2 T82 28
valid_sources[0x6e] 402 1 T62 3 T82 5 T90 1
valid_sources[0x6f] 870 1 T212 1 T205 2 T184 1
valid_sources[0x70] 323 1 T244 1 T176 1 T61 2
valid_sources[0x71] 415 1 T150 7 T7 1 T62 2
valid_sources[0x72] 515 1 T224 1 T62 2 T90 2
valid_sources[0x73] 336 1 T61 3 T62 3 T90 3
valid_sources[0x74] 392 1 T84 1 T239 1 T245 1
valid_sources[0x75] 691 1 T224 2 T61 4 T62 2
valid_sources[0x76] 411 1 T43 1 T177 1 T193 1
valid_sources[0x77] 428 1 T177 1 T62 2 T86 7
valid_sources[0x78] 305 1 T55 2 T71 1 T178 1
valid_sources[0x79] 437 1 T44 2 T61 1 T76 30
valid_sources[0x7a] 469 1 T13 1 T61 1 T64 5
valid_sources[0x7b] 354 1 T71 3 T246 1 T22 1
valid_sources[0x7c] 576 1 T40 1 T62 2 T90 2
valid_sources[0x7d] 390 1 T175 1 T171 1 T61 1
valid_sources[0x7e] 377 1 T184 1 T199 1 T61 4
valid_sources[0x7f] 562 1 T58 1 T61 2 T85 2
valid_sources[0x80] 556 1 T50 1 T61 1 T62 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 30749 1 T58 17 T63 4 T61 65
values[0x0] all_enables biggest_size 42558 1 T1 2 T2 1 T3 4
values[0x1] all_enables biggest_size 42611 1 T1 5 T4 2 T5 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%