Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	763115	1		T1	11		T2	1		T3	2
full_word	685038	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1447813	1		T1	13		T2	2		T3	3
auto[TlIntgErrCmd]	128	1		T59	9		T87	11		T96	11
auto[TlIntgErrData]	112	1		T59	8		T87	5		T96	5
auto[TlIntgErrBoth]	100	1		T59	3		T87	4		T96	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	537789	1		T2	1		T4	7		T5	13
auto[1]	910364	1		T1	13		T2	1		T3	3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	218657	1		T2	1		T4	2		T5	6
auto[TlIntgErrNone]	partial	auto[1]	544143	1		T1	11		T3	2		T4	9
auto[TlIntgErrNone]	full_word	auto[0]	318978	1		T4	5		T5	7		T26	1
auto[TlIntgErrNone]	full_word	auto[1]	366035	1		T1	2		T2	1		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	54	1		T59	2		T87	4		T96	6
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T59	7		T87	7		T96	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T127	1		T160	1		T161	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T127	1		T156	1		T162	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T59	2		T87	1		T96	2
auto[TlIntgErrData]	partial	auto[1]	57	1		T59	4		T87	3		T96	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T87	1		T157	1		T162	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T59	2		T160	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1		T59	2		T96	2		T124	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T59	1		T87	4		T96	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T161	1		T156	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T155	1		T163	1		T162	1