Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9797388 |
9796056 |
0 |
0 |
selKnown1 |
55378581 |
55377249 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9797388 |
9796056 |
0 |
0 |
T1 |
19170 |
19166 |
0 |
0 |
T2 |
2298 |
2294 |
0 |
0 |
T3 |
19049 |
19045 |
0 |
0 |
T4 |
25692 |
25688 |
0 |
0 |
T5 |
41957 |
41953 |
0 |
0 |
T10 |
247203 |
247199 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
0 |
12 |
0 |
0 |
T30 |
1929 |
1925 |
0 |
0 |
T31 |
0 |
6 |
0 |
0 |
T36 |
483 |
479 |
0 |
0 |
T42 |
522 |
518 |
0 |
0 |
T43 |
12937 |
12933 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55378581 |
55377249 |
0 |
0 |
T1 |
32678 |
32674 |
0 |
0 |
T2 |
4032 |
4028 |
0 |
0 |
T3 |
49105 |
49101 |
0 |
0 |
T4 |
133040 |
133036 |
0 |
0 |
T5 |
437126 |
437122 |
0 |
0 |
T10 |
250200 |
250197 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
0 |
12 |
0 |
0 |
T30 |
24865 |
24861 |
0 |
0 |
T31 |
0 |
6 |
0 |
0 |
T36 |
4100 |
4096 |
0 |
0 |
T42 |
4174 |
4170 |
0 |
0 |
T43 |
165064 |
165060 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2893259 |
2893036 |
0 |
0 |
selKnown1 |
48474983 |
48474760 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2893259 |
2893036 |
0 |
0 |
T1 |
9580 |
9579 |
0 |
0 |
T2 |
1148 |
1147 |
0 |
0 |
T3 |
9519 |
9518 |
0 |
0 |
T4 |
12843 |
12842 |
0 |
0 |
T5 |
20969 |
20968 |
0 |
0 |
T10 |
123600 |
123599 |
0 |
0 |
T30 |
963 |
962 |
0 |
0 |
T36 |
240 |
239 |
0 |
0 |
T42 |
260 |
259 |
0 |
0 |
T43 |
6463 |
6462 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48474983 |
48474760 |
0 |
0 |
T1 |
23090 |
23089 |
0 |
0 |
T2 |
2882 |
2881 |
0 |
0 |
T3 |
39578 |
39577 |
0 |
0 |
T4 |
120191 |
120190 |
0 |
0 |
T5 |
416151 |
416150 |
0 |
0 |
T10 |
126598 |
126598 |
0 |
0 |
T30 |
23900 |
23899 |
0 |
0 |
T36 |
3858 |
3857 |
0 |
0 |
T42 |
3912 |
3911 |
0 |
0 |
T43 |
158599 |
158598 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
607 |
384 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
4 |
3 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T26 |
0 |
2 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
1 |
0 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
T55 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
576 |
353 |
0 |
0 |
T1 |
4 |
3 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
3 |
2 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T26 |
0 |
2 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
1 |
0 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
T55 |
0 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6901451 |
6901008 |
0 |
0 |
selKnown1 |
6901231 |
6900788 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6901451 |
6901008 |
0 |
0 |
T1 |
9580 |
9579 |
0 |
0 |
T2 |
1148 |
1147 |
0 |
0 |
T3 |
9520 |
9519 |
0 |
0 |
T4 |
12843 |
12842 |
0 |
0 |
T5 |
20969 |
20968 |
0 |
0 |
T10 |
123601 |
123600 |
0 |
0 |
T30 |
964 |
963 |
0 |
0 |
T36 |
241 |
240 |
0 |
0 |
T42 |
260 |
259 |
0 |
0 |
T43 |
6464 |
6463 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6901231 |
6900788 |
0 |
0 |
T1 |
9580 |
9579 |
0 |
0 |
T2 |
1148 |
1147 |
0 |
0 |
T3 |
9519 |
9518 |
0 |
0 |
T4 |
12843 |
12842 |
0 |
0 |
T5 |
20969 |
20968 |
0 |
0 |
T10 |
123600 |
123599 |
0 |
0 |
T30 |
963 |
962 |
0 |
0 |
T36 |
240 |
239 |
0 |
0 |
T42 |
260 |
259 |
0 |
0 |
T43 |
6463 |
6462 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2071 |
1628 |
0 |
0 |
selKnown1 |
1791 |
1348 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2071 |
1628 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
15 |
14 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T26 |
0 |
2 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
9 |
8 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1791 |
1348 |
0 |
0 |
T1 |
4 |
3 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
3 |
2 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T26 |
0 |
2 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
1 |
0 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
T55 |
0 |
7 |
0 |
0 |