Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_lc_hw_debug_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_lc_dft_en	100.00	100.00					100.00
tb.dut.u_lc_en_sync_copies	100.00	100.00					100.00
tb.dut.u_pm_en_sync	100.00	100.00					100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_en_sync_copies

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_pm_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.13	86.27	72.22		57.14	75.00	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.81	98.04	77.78		85.71	87.50	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_en_sync_copies

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	5	5

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_pm_en_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1338	1338	0	0
OutputsKnown_A	290849898	290616936	0	0
gen_flops.OutputDelay_A	145424949	145303284	0	2007
gen_no_flops.OutputDelay_A	145424949	145308468	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1338	1338	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T10	6	6	0	0
T30	6	6	0	0
T36	6	6	0	0
T42	6	6	0	0
T43	6	6	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290849898	290616936	0	0
T1	138540	136716	0	0
T2	17292	16746	0	0
T3	237468	235746	0	0
T4	721146	719964	0	0
T5	2496906	2495472	0	0
T10	759588	759546	0	0
T30	143400	142932	0	0
T36	23148	22764	0	0
T42	23472	23148	0	0
T43	951594	951252	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145424949	145303284	0	2007
T1	69270	68322	0	9
T2	8646	8364	0	9
T3	118734	117837	0	9
T4	360573	359955	0	9
T5	1248453	1247709	0	9
T10	379794	379773	0	9
T30	71700	71457	0	9
T36	11574	11373	0	9
T42	11736	11565	0	9
T43	475797	475617	0	9

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145424949	145308468	0	0
T1	69270	68358	0	0
T2	8646	8373	0	0
T3	118734	117873	0	0
T4	360573	359982	0	0
T5	1248453	1247736	0	0
T10	379794	379773	0	0
T30	71700	71466	0	0
T36	11574	11382	0	0
T42	11736	11574	0	0
T43	475797	475626	0	0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	223	223	0	0
OutputsKnown_A	48474983	48436156	0	0
gen_flops.OutputDelay_A	48474983	48434428	0	669

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223	223	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T36	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48434428	0	669
T1	23090	22774	0	3
T2	2882	2788	0	3
T3	39578	39279	0	3
T4	120191	119985	0	3
T5	416151	415903	0	3
T10	126598	126591	0	3
T30	23900	23819	0	3
T36	3858	3791	0	3
T42	3912	3855	0	3
T43	158599	158539	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	223	223	0	0
OutputsKnown_A	48474983	48436156	0	0
gen_flops.OutputDelay_A	48474983	48434428	0	669

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223	223	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T36	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48434428	0	669
T1	23090	22774	0	3
T2	2882	2788	0	3
T3	39578	39279	0	3
T4	120191	119985	0	3
T5	416151	415903	0	3
T10	126598	126591	0	3
T30	23900	23819	0	3
T36	3858	3791	0	3
T42	3912	3855	0	3
T43	158599	158539	0	3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	5	5

---

Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	223	223	0	0
OutputsKnown_A	48474983	48436156	0	0
gen_no_flops.OutputDelay_A	48474983	48436156	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223	223	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T36	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

Line Coverage for Instance : tb.dut.u_pm_en_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.u_pm_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	223	223	0	0
OutputsKnown_A	48474983	48436156	0	0
gen_flops.OutputDelay_A	48474983	48434428	0	669

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223	223	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T36	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48434428	0	669
T1	23090	22774	0	3
T2	2882	2788	0	3
T3	39578	39279	0	3
T4	120191	119985	0	3
T5	416151	415903	0	3
T10	126598	126591	0	3
T30	23900	23819	0	3
T36	3858	3791	0	3
T42	3912	3855	0	3
T43	158599	158539	0	3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	223	223	0	0
OutputsKnown_A	48474983	48436156	0	0
gen_no_flops.OutputDelay_A	48474983	48436156	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223	223	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T36	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	223	223	0	0
OutputsKnown_A	48474983	48436156	0	0
gen_no_flops.OutputDelay_A	48474983	48436156	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223	223	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T36	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48474983	48436156	0	0
T1	23090	22786	0	0
T2	2882	2791	0	0
T3	39578	39291	0	0
T4	120191	119994	0	0
T5	416151	415912	0	0
T10	126598	126591	0	0
T30	23900	23822	0	0
T36	3858	3794	0	0
T42	3912	3858	0	0
T43	158599	158542	0	0