Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	195946	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	527912	1		T3	1		T4	3		T5	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	445527	1		T4	1		T37	1		T30	6
values[0x0]	132132	1		T3	2		T4	3		T5	6
values[0x1]	146199	1		T3	2		T4	3		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144937	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	578921	1		T3	2		T4	3		T5	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2749	1		T11	1		T44	1		T60	7
valid_sources[0x01]	2700	1		T8	1		T150	3		T60	5
valid_sources[0x02]	2653	1		T132	28		T60	8		T61	15
valid_sources[0x03]	2721	1		T45	1		T169	1		T21	2
valid_sources[0x04]	2662	1		T11	1		T137	3		T60	5
valid_sources[0x05]	2686	1		T18	1		T21	2		T60	22
valid_sources[0x06]	2692	1		T60	6		T61	12		T62	25
valid_sources[0x07]	2740	1		T15	2		T18	1		T60	5
valid_sources[0x08]	3081	1		T31	1		T170	6		T60	8
valid_sources[0x09]	3432	1		T31	1		T171	1		T47	1
valid_sources[0x0a]	2630	1		T4	1		T141	1		T60	15
valid_sources[0x0b]	2525	1		T172	1		T44	1		T60	14
valid_sources[0x0c]	3063	1		T44	2		T41	1		T60	4
valid_sources[0x0d]	2503	1		T173	1		T60	5		T61	22
valid_sources[0x0e]	5479	1		T44	2		T60	9		T61	12
valid_sources[0x0f]	2634	1		T60	10		T61	17		T62	49
valid_sources[0x10]	2722	1		T60	9		T61	15		T62	25
valid_sources[0x11]	3788	1		T50	4		T147	3		T60	6
valid_sources[0x12]	2577	1		T60	7		T61	22		T62	31
valid_sources[0x13]	2887	1		T60	7		T61	10		T62	31
valid_sources[0x14]	2660	1		T11	1		T60	4		T61	16
valid_sources[0x15]	2850	1		T44	1		T60	9		T61	18
valid_sources[0x16]	2722	1		T59	1		T60	7		T61	19
valid_sources[0x17]	3290	1		T169	1		T141	1		T21	1
valid_sources[0x18]	2904	1		T171	2		T174	9		T60	7
valid_sources[0x19]	3327	1		T11	2		T170	7		T60	7
valid_sources[0x1a]	2679	1		T60	11		T61	19		T62	21
valid_sources[0x1b]	2615	1		T6	1		T141	2		T60	5
valid_sources[0x1c]	2502	1		T60	4		T61	16		T62	17
valid_sources[0x1d]	2642	1		T135	1		T18	1		T60	7
valid_sources[0x1e]	2610	1		T36	1		T45	3		T175	14
valid_sources[0x1f]	2815	1		T29	1		T8	1		T11	1
valid_sources[0x20]	2675	1		T60	7		T61	17		T62	14
valid_sources[0x21]	2843	1		T11	1		T50	1		T41	1
valid_sources[0x22]	2727	1		T60	12		T61	17		T62	11
valid_sources[0x23]	2884	1		T41	4		T60	10		T61	9
valid_sources[0x24]	3055	1		T17	7		T60	9		T61	16
valid_sources[0x25]	2679	1		T44	2		T18	1		T176	46
valid_sources[0x26]	2646	1		T24	1		T60	9		T61	9
valid_sources[0x27]	2499	1		T137	3		T169	1		T147	2
valid_sources[0x28]	10301	1		T11	1		T172	1		T44	1
valid_sources[0x29]	2544	1		T19	6		T60	14		T61	17
valid_sources[0x2a]	2709	1		T60	6		T61	6		T62	32
valid_sources[0x2b]	3215	1		T172	1		T60	4		T61	11
valid_sources[0x2c]	2805	1		T11	1		T60	8		T61	12
valid_sources[0x2d]	2796	1		T60	13		T61	16		T62	35
valid_sources[0x2e]	2740	1		T60	8		T61	13		T62	37
valid_sources[0x2f]	3094	1		T170	1		T60	14		T61	14
valid_sources[0x30]	3157	1		T23	3		T147	3		T21	2
valid_sources[0x31]	2552	1		T10	33		T141	1		T60	8
valid_sources[0x32]	2640	1		T60	9		T61	19		T62	6
valid_sources[0x33]	3104	1		T151	1		T177	2		T60	11
valid_sources[0x34]	3087	1		T60	5		T61	18		T62	33
valid_sources[0x35]	2903	1		T41	4		T60	6		T61	12
valid_sources[0x36]	2658	1		T141	2		T60	11		T61	15
valid_sources[0x37]	2865	1		T18	1		T41	3		T60	11
valid_sources[0x38]	2831	1		T14	1		T172	2		T169	1
valid_sources[0x39]	2606	1		T135	5		T60	8		T61	24
valid_sources[0x3a]	2960	1		T60	2		T61	17		T62	24
valid_sources[0x3b]	2693	1		T31	2		T60	6		T61	12
valid_sources[0x3c]	2744	1		T60	13		T61	14		T62	13
valid_sources[0x3d]	2675	1		T178	2		T179	1		T60	11
valid_sources[0x3e]	2823	1		T31	1		T8	3		T169	1
valid_sources[0x3f]	2564	1		T60	4		T61	16		T62	30
valid_sources[0x40]	2832	1		T8	1		T11	1		T60	12
valid_sources[0x41]	2661	1		T14	5		T60	9		T61	12
valid_sources[0x42]	2619	1		T60	9		T61	13		T62	39
valid_sources[0x43]	2499	1		T44	1		T60	12		T61	17
valid_sources[0x44]	2709	1		T147	3		T21	1		T175	3
valid_sources[0x45]	2892	1		T24	1		T60	7		T61	9
valid_sources[0x46]	2624	1		T141	1		T60	10		T61	16
valid_sources[0x47]	2851	1		T60	18		T61	13		T62	21
valid_sources[0x48]	2832	1		T169	1		T60	2		T61	13
valid_sources[0x49]	3015	1		T172	1		T44	1		T141	1
valid_sources[0x4a]	2688	1		T29	2		T50	3		T60	9
valid_sources[0x4b]	2763	1		T31	2		T44	1		T60	13
valid_sources[0x4c]	2863	1		T45	2		T44	1		T60	4
valid_sources[0x4d]	2589	1		T60	4		T61	11		T62	34
valid_sources[0x4e]	4870	1		T11	1		T60	6		T61	10
valid_sources[0x4f]	2869	1		T141	1		T60	12		T61	15
valid_sources[0x50]	2712	1		T41	2		T173	3		T60	12
valid_sources[0x51]	2771	1		T60	9		T61	8		T62	49
valid_sources[0x52]	2685	1		T11	1		T60	6		T61	23
valid_sources[0x53]	2598	1		T11	1		T60	6		T61	16
valid_sources[0x54]	2641	1		T60	11		T61	11		T62	36
valid_sources[0x55]	2994	1		T44	1		T60	4		T61	10
valid_sources[0x56]	2706	1		T60	7		T61	18		T62	9
valid_sources[0x57]	2700	1		T18	1		T60	6		T61	19
valid_sources[0x58]	2599	1		T60	6		T61	16		T62	14
valid_sources[0x59]	2572	1		T8	1		T18	1		T47	1
valid_sources[0x5a]	2687	1		T147	2		T21	1		T175	2
valid_sources[0x5b]	2516	1		T18	1		T136	8		T47	1
valid_sources[0x5c]	3003	1		T22	1		T8	1		T46	9
valid_sources[0x5d]	2574	1		T50	2		T172	1		T44	1
valid_sources[0x5e]	2686	1		T135	4		T60	4		T61	13
valid_sources[0x5f]	2585	1		T60	10		T61	13		T62	19
valid_sources[0x60]	2749	1		T169	1		T24	1		T60	8
valid_sources[0x61]	2955	1		T172	1		T47	2		T60	16
valid_sources[0x62]	2630	1		T44	1		T60	8		T61	15
valid_sources[0x63]	2535	1		T31	2		T60	7		T61	11
valid_sources[0x64]	3057	1		T31	1		T45	2		T21	1
valid_sources[0x65]	2451	1		T169	1		T60	7		T61	11
valid_sources[0x66]	2918	1		T11	2		T60	12		T61	20
valid_sources[0x67]	2857	1		T44	1		T169	1		T60	11
valid_sources[0x68]	2688	1		T37	2		T60	8		T61	15
valid_sources[0x69]	2884	1		T134	1		T18	1		T24	1
valid_sources[0x6a]	2943	1		T171	1		T60	4		T61	15
valid_sources[0x6b]	3161	1		T60	13		T61	14		T62	21
valid_sources[0x6c]	2652	1		T135	3		T60	11		T61	14
valid_sources[0x6d]	2729	1		T44	2		T18	1		T24	1
valid_sources[0x6e]	2983	1		T31	1		T44	2		T60	10
valid_sources[0x6f]	2978	1		T18	1		T60	7		T61	12
valid_sources[0x70]	2889	1		T14	4		T141	2		T171	1
valid_sources[0x71]	2585	1		T18	2		T175	4		T60	14
valid_sources[0x72]	2673	1		T141	2		T60	7		T61	15
valid_sources[0x73]	3180	1		T141	1		T24	1		T60	7
valid_sources[0x74]	3004	1		T50	4		T60	5		T61	11
valid_sources[0x75]	2481	1		T18	1		T41	1		T60	6
valid_sources[0x76]	2551	1		T41	4		T173	4		T60	13
valid_sources[0x77]	3175	1		T170	1		T60	6		T61	13
valid_sources[0x78]	2553	1		T4	2		T147	3		T60	11
valid_sources[0x79]	2576	1		T50	2		T41	1		T60	6
valid_sources[0x7a]	2484	1		T44	1		T60	6		T61	20
valid_sources[0x7b]	2880	1		T172	3		T60	10		T61	14
valid_sources[0x7c]	2822	1		T8	1		T180	1		T60	5
valid_sources[0x7d]	2881	1		T11	1		T44	1		T24	1
valid_sources[0x7e]	2646	1		T31	1		T60	10		T61	22
valid_sources[0x7f]	2723	1		T24	1		T173	1		T60	7
valid_sources[0x80]	2802	1		T8	1		T60	11		T61	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

268817

1

T4

1

T37

1

T30

3

values[0x0]

all_enables

biggest_size

129429

1

T3

1

T4

1

T5

3

values[0x1]

all_enables

biggest_size

129666

1

T4

1

T22

1

T37

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5345	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	38659	1		T1	5		T2	1		T3	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14457	1		T60	208		T61	922		T62	31
values[0x0]	14469	1		T1	10		T2	1		T3	2
values[0x1]	15078	1		T1	11		T3	5		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3893	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	40111	1		T1	7		T2	1		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	369	1		T181	5		T15	1		T182	3
valid_sources[0x01]	96	1		T62	4		T79	4		T81	4
valid_sources[0x02]	170	1		T71	1		T183	1		T78	8
valid_sources[0x03]	214	1		T184	3		T78	10		T79	3
valid_sources[0x04]	85	1		T185	1		T148	1		T78	1
valid_sources[0x05]	209	1		T174	1		T61	1		T78	1
valid_sources[0x06]	130	1		T186	1		T187	4		T182	1
valid_sources[0x07]	647	1		T188	1		T189	1		T190	1
valid_sources[0x08]	143	1		T86	1		T81	3		T89	1
valid_sources[0x09]	517	1		T68	1		T191	11		T192	1
valid_sources[0x0a]	69	1		T193	5		T194	1		T78	3
valid_sources[0x0b]	150	1		T29	2		T195	13		T60	1
valid_sources[0x0c]	109	1		T196	1		T197	1		T78	2
valid_sources[0x0d]	190	1		T78	7		T79	1		T81	1
valid_sources[0x0e]	115	1		T198	3		T188	1		T199	1
valid_sources[0x0f]	84	1		T200	1		T201	1		T62	6
valid_sources[0x10]	94	1		T202	2		T194	1		T78	4
valid_sources[0x11]	80	1		T78	4		T83	2		T102	4
valid_sources[0x12]	278	1		T68	1		T203	1		T62	3
valid_sources[0x13]	117	1		T142	3		T133	1		T78	2
valid_sources[0x14]	106	1		T25	1		T78	2		T79	2
valid_sources[0x15]	92	1		T189	1		T174	1		T204	1
valid_sources[0x16]	82	1		T39	1		T44	1		T89	1
valid_sources[0x17]	251	1		T148	1		T133	1		T205	6
valid_sources[0x18]	171	1		T48	2		T8	5		T60	1
valid_sources[0x19]	261	1		T186	1		T61	1		T78	3
valid_sources[0x1a]	97	1		T206	1		T179	1		T207	1
valid_sources[0x1b]	287	1		T36	1		T208	2		T60	1
valid_sources[0x1c]	106	1		T209	1		T76	1		T40	1
valid_sources[0x1d]	254	1		T210	1		T211	1		T60	1
valid_sources[0x1e]	104	1		T206	1		T207	2		T78	3
valid_sources[0x1f]	235	1		T60	1		T61	131		T79	5
valid_sources[0x20]	84	1		T33	1		T34	1		T80	1
valid_sources[0x21]	172	1		T212	1		T185	1		T213	1
valid_sources[0x22]	235	1		T139	1		T196	1		T18	1
valid_sources[0x23]	178	1		T28	1		T134	3		T214	1
valid_sources[0x24]	143	1		T174	1		T208	2		T78	14
valid_sources[0x25]	146	1		T215	1		T216	1		T217	1
valid_sources[0x26]	169	1		T11	2		T218	1		T79	4
valid_sources[0x27]	297	1		T17	2		T219	1		T220	1
valid_sources[0x28]	146	1		T44	1		T189	1		T78	3
valid_sources[0x29]	125	1		T61	1		T79	10		T83	7
valid_sources[0x2a]	108	1		T126	1		T15	1		T134	2
valid_sources[0x2b]	97	1		T188	2		T192	1		T78	1
valid_sources[0x2c]	170	1		T196	1		T44	1		T214	4
valid_sources[0x2d]	434	1		T148	1		T214	2		T175	9
valid_sources[0x2e]	110	1		T221	1		T61	1		T78	7
valid_sources[0x2f]	118	1		T217	2		T78	3		T79	1
valid_sources[0x30]	90	1		T4	4		T171	7		T222	1
valid_sources[0x31]	82	1		T223	1		T78	14		T81	1
valid_sources[0x32]	78	1		T146	1		T224	1		T189	1
valid_sources[0x33]	78	1		T3	1		T189	4		T79	11
valid_sources[0x34]	223	1		T44	1		T182	1		T78	5
valid_sources[0x35]	311	1		T78	3		T79	6		T90	3
valid_sources[0x36]	102	1		T5	1		T78	1		T81	3
valid_sources[0x37]	100	1		T148	1		T210	1		T78	8
valid_sources[0x38]	345	1		T68	1		T61	1		T78	16
valid_sources[0x39]	187	1		T14	3		T143	4		T78	1
valid_sources[0x3a]	161	1		T172	6		T17	3		T221	1
valid_sources[0x3b]	457	1		T182	1		T192	1		T189	1
valid_sources[0x3c]	80	1		T137	2		T179	1		T190	1
valid_sources[0x3d]	137	1		T3	2		T14	2		T78	3
valid_sources[0x3e]	99	1		T193	1		T60	3		T78	10
valid_sources[0x3f]	201	1		T5	1		T16	1		T218	1
valid_sources[0x40]	89	1		T78	3		T81	3		T83	5
valid_sources[0x41]	121	1		T194	1		T60	8		T78	4
valid_sources[0x42]	81	1		T189	2		T173	1		T82	1
valid_sources[0x43]	97	1		T34	1		T15	1		T225	1
valid_sources[0x44]	102	1		T126	1		T220	1		T213	1
valid_sources[0x45]	115	1		T33	1		T226	1		T144	2
valid_sources[0x46]	403	1		T227	1		T199	2		T78	1
valid_sources[0x47]	341	1		T193	1		T137	1		T60	4
valid_sources[0x48]	273	1		T48	1		T147	1		T78	3
valid_sources[0x49]	57	1		T60	1		T78	2		T79	3
valid_sources[0x4a]	61	1		T221	1		T173	1		T228	1
valid_sources[0x4b]	101	1		T229	2		T198	6		T230	2
valid_sources[0x4c]	75	1		T231	1		T204	3		T78	7
valid_sources[0x4d]	503	1		T202	2		T232	6		T61	293
valid_sources[0x4e]	108	1		T44	1		T233	1		T190	2
valid_sources[0x4f]	224	1		T21	1		T192	1		T234	1
valid_sources[0x50]	180	1		T194	1		T234	1		T81	1
valid_sources[0x51]	208	1		T1	1		T23	7		T218	1
valid_sources[0x52]	117	1		T1	2		T235	2		T236	1
valid_sources[0x53]	176	1		T1	1		T33	3		T214	1
valid_sources[0x54]	114	1		T221	1		T206	1		T180	1
valid_sources[0x55]	121	1		T186	1		T194	2		T78	3
valid_sources[0x56]	117	1		T11	1		T141	1		T235	1
valid_sources[0x57]	273	1		T208	1		T79	3		T80	1
valid_sources[0x58]	163	1		T144	2		T237	1		T220	1
valid_sources[0x59]	152	1		T37	1		T189	1		T60	1
valid_sources[0x5a]	206	1		T23	1		T238	1		T174	1
valid_sources[0x5b]	95	1		T210	1		T196	2		T174	1
valid_sources[0x5c]	163	1		T239	1		T60	1		T78	5
valid_sources[0x5d]	237	1		T208	1		T61	4		T78	2
valid_sources[0x5e]	99	1		T38	1		T235	1		T20	1
valid_sources[0x5f]	145	1		T218	1		T78	3		T79	13
valid_sources[0x60]	79	1		T236	2		T177	1		T78	7
valid_sources[0x61]	265	1		T15	1		T210	1		T79	4
valid_sources[0x62]	105	1		T15	2		T221	2		T141	2
valid_sources[0x63]	101	1		T202	1		T78	3		T79	2
valid_sources[0x64]	93	1		T9	1		T214	1		T221	1
valid_sources[0x65]	328	1		T235	1		T78	3		T79	1
valid_sources[0x66]	104	1		T78	1		T79	1		T86	1
valid_sources[0x67]	117	1		T29	1		T240	4		T60	1
valid_sources[0x68]	450	1		T77	1		T60	5		T61	1
valid_sources[0x69]	357	1		T4	1		T28	1		T147	7
valid_sources[0x6a]	223	1		T17	2		T221	1		T204	1
valid_sources[0x6b]	271	1		T126	1		T78	1		T79	2
valid_sources[0x6c]	161	1		T185	1		T78	5		T86	1
valid_sources[0x6d]	161	1		T2	1		T9	2		T194	1
valid_sources[0x6e]	102	1		T48	1		T137	2		T241	1
valid_sources[0x6f]	102	1		T242	1		T60	1		T78	9
valid_sources[0x70]	423	1		T202	1		T206	1		T55	1
valid_sources[0x71]	74	1		T3	2		T174	1		T78	1
valid_sources[0x72]	70	1		T33	1		T243	12		T78	4
valid_sources[0x73]	121	1		T18	1		T78	8		T86	1
valid_sources[0x74]	76	1		T4	1		T78	1		T82	1
valid_sources[0x75]	302	1		T57	1		T244	2		T245	4
valid_sources[0x76]	120	1		T246	1		T196	2		T183	1
valid_sources[0x77]	122	1		T196	1		T79	10		T81	1
valid_sources[0x78]	89	1		T5	1		T170	1		T24	6
valid_sources[0x79]	83	1		T148	1		T78	2		T81	2
valid_sources[0x7a]	115	1		T126	1		T235	1		T247	1
valid_sources[0x7b]	86	1		T189	1		T241	1		T79	13
valid_sources[0x7c]	323	1		T190	1		T79	12		T86	1
valid_sources[0x7d]	186	1		T221	1		T182	1		T192	1
valid_sources[0x7e]	130	1		T27	1		T210	1		T248	1
valid_sources[0x7f]	105	1		T126	1		T202	1		T235	3
valid_sources[0x80]	420	1		T218	1		T183	1		T61	81

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11427

1

T60

186

T61

883

T62

12

values[0x0]

all_enables

biggest_size

13706

1

T1

4

T2

1

T3

2

values[0x1]

all_enables

biggest_size

13526

1

T1

1

T3

5

T7

1