Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
306031 |
1 |
|
T3 |
3 |
|
T4 |
4 |
|
T5 |
5 |
full_word |
532307 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
3 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
838058 |
1 |
|
T3 |
4 |
|
T4 |
7 |
|
T5 |
8 |
auto[TlIntgErrCmd] |
106 |
1 |
|
T62 |
1 |
|
T96 |
9 |
|
T129 |
6 |
auto[TlIntgErrData] |
83 |
1 |
|
T62 |
2 |
|
T96 |
4 |
|
T129 |
9 |
auto[TlIntgErrBoth] |
91 |
1 |
|
T62 |
7 |
|
T96 |
7 |
|
T129 |
5 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
450762 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T30 |
6 |
auto[1] |
387576 |
1 |
|
T3 |
4 |
|
T4 |
6 |
|
T5 |
8 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
181270 |
1 |
|
T30 |
3 |
|
T42 |
5 |
|
T11 |
6 |
auto[TlIntgErrNone] |
partial |
auto[1] |
124506 |
1 |
|
T3 |
3 |
|
T4 |
4 |
|
T5 |
5 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
269360 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T30 |
3 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
262922 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
3 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
34 |
1 |
|
T62 |
1 |
|
T96 |
1 |
|
T129 |
3 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
64 |
1 |
|
T96 |
6 |
|
T129 |
3 |
|
T152 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
4 |
1 |
|
T96 |
1 |
|
T158 |
1 |
|
T159 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
T96 |
1 |
|
T160 |
1 |
|
T161 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
45 |
1 |
|
T62 |
1 |
|
T96 |
3 |
|
T129 |
5 |
auto[TlIntgErrData] |
partial |
auto[1] |
29 |
1 |
|
T62 |
1 |
|
T129 |
4 |
|
T158 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
6 |
1 |
|
T160 |
1 |
|
T156 |
1 |
|
T157 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
3 |
1 |
|
T96 |
1 |
|
T162 |
1 |
|
T163 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
41 |
1 |
|
T62 |
4 |
|
T96 |
2 |
|
T129 |
3 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
42 |
1 |
|
T62 |
2 |
|
T96 |
4 |
|
T129 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
2 |
1 |
|
T96 |
1 |
|
T164 |
1 |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
6 |
1 |
|
T62 |
1 |
|
T165 |
1 |
|
T166 |
1 |