Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	121710536	38176	0	0
late_debug_enable_rd_A	121710536	8913	0	0
late_debug_enable_regwen_rd_A	121710536	5991	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121710536	38176	0	0
T60	207452	1495	0	0
T61	910688	2901	0	0
T62	348613	3	0	0
T78	10034	636	0	0
T79	130725	986	0	0
T80	9643	19	0	0
T81	27230	471	0	0
T82	8782	398	0	0
T83	31645	625	0	0
T96	99624	6	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121710536	8913	0	0
T62	348613	18	0	0
T80	9643	9	0	0
T82	8782	35	0	0
T83	31645	212	0	0
T84	23050	240	0	0
T85	28497	327	0	0
T88	9427	8	0	0
T89	50942	36	0	0
T95	9101	5	0	0
T127	22777	55	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121710536	5991	0	0
T62	348613	16	0	0
T80	9643	12	0	0
T82	8782	111	0	0
T83	31645	178	0	0
T84	23050	242	0	0
T85	28497	223	0	0
T88	9427	9	0	0
T89	50942	74	0	0
T95	9101	3	0	0
T127	22777	81	0	0