Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
49113192 |
0 |
0 |
T1 |
3359 |
3290 |
0 |
0 |
T2 |
159748 |
159689 |
0 |
0 |
T3 |
435821 |
435544 |
0 |
0 |
T4 |
21720 |
21439 |
0 |
0 |
T7 |
54901 |
54851 |
0 |
0 |
T13 |
27822 |
27757 |
0 |
0 |
T26 |
14282 |
14146 |
0 |
0 |
T27 |
31521 |
31436 |
0 |
0 |
T48 |
2492 |
2416 |
0 |
0 |
T49 |
192424 |
192374 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
49113192 |
0 |
0 |
T1 |
3359 |
3290 |
0 |
0 |
T2 |
159748 |
159689 |
0 |
0 |
T3 |
435821 |
435544 |
0 |
0 |
T4 |
21720 |
21439 |
0 |
0 |
T7 |
54901 |
54851 |
0 |
0 |
T13 |
27822 |
27757 |
0 |
0 |
T26 |
14282 |
14146 |
0 |
0 |
T27 |
31521 |
31436 |
0 |
0 |
T48 |
2492 |
2416 |
0 |
0 |
T49 |
192424 |
192374 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
49113192 |
0 |
0 |
T1 |
3359 |
3290 |
0 |
0 |
T2 |
159748 |
159689 |
0 |
0 |
T3 |
435821 |
435544 |
0 |
0 |
T4 |
21720 |
21439 |
0 |
0 |
T7 |
54901 |
54851 |
0 |
0 |
T13 |
27822 |
27757 |
0 |
0 |
T26 |
14282 |
14146 |
0 |
0 |
T27 |
31521 |
31436 |
0 |
0 |
T48 |
2492 |
2416 |
0 |
0 |
T49 |
192424 |
192374 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
49113192 |
0 |
0 |
T1 |
3359 |
3290 |
0 |
0 |
T2 |
159748 |
159689 |
0 |
0 |
T3 |
435821 |
435544 |
0 |
0 |
T4 |
21720 |
21439 |
0 |
0 |
T7 |
54901 |
54851 |
0 |
0 |
T13 |
27822 |
27757 |
0 |
0 |
T26 |
14282 |
14146 |
0 |
0 |
T27 |
31521 |
31436 |
0 |
0 |
T48 |
2492 |
2416 |
0 |
0 |
T49 |
192424 |
192374 |
0 |
0 |