Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
19797 |
0 |
0 |
T1 |
3359 |
1 |
0 |
0 |
T2 |
159748 |
62 |
0 |
0 |
T3 |
435821 |
71 |
0 |
0 |
T4 |
21720 |
93 |
0 |
0 |
T7 |
54901 |
131 |
0 |
0 |
T13 |
27822 |
141 |
0 |
0 |
T26 |
14282 |
53 |
0 |
0 |
T27 |
31521 |
46 |
0 |
0 |
T48 |
2492 |
1 |
0 |
0 |
T49 |
192424 |
140 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
48895761 |
0 |
0 |
T1 |
3359 |
3153 |
0 |
0 |
T2 |
159748 |
159372 |
0 |
0 |
T3 |
435821 |
433629 |
0 |
0 |
T4 |
21720 |
21110 |
0 |
0 |
T7 |
54901 |
54827 |
0 |
0 |
T13 |
27822 |
27740 |
0 |
0 |
T26 |
14282 |
14083 |
0 |
0 |
T27 |
31521 |
31390 |
0 |
0 |
T48 |
2492 |
2393 |
0 |
0 |
T49 |
192424 |
192195 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
48895761 |
0 |
0 |
T1 |
3359 |
3153 |
0 |
0 |
T2 |
159748 |
159372 |
0 |
0 |
T3 |
435821 |
433629 |
0 |
0 |
T4 |
21720 |
21110 |
0 |
0 |
T7 |
54901 |
54827 |
0 |
0 |
T13 |
27822 |
27740 |
0 |
0 |
T26 |
14282 |
14083 |
0 |
0 |
T27 |
31521 |
31390 |
0 |
0 |
T48 |
2492 |
2393 |
0 |
0 |
T49 |
192424 |
192195 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
48895761 |
0 |
0 |
T1 |
3359 |
3153 |
0 |
0 |
T2 |
159748 |
159372 |
0 |
0 |
T3 |
435821 |
433629 |
0 |
0 |
T4 |
21720 |
21110 |
0 |
0 |
T7 |
54901 |
54827 |
0 |
0 |
T13 |
27822 |
27740 |
0 |
0 |
T26 |
14282 |
14083 |
0 |
0 |
T27 |
31521 |
31390 |
0 |
0 |
T48 |
2492 |
2393 |
0 |
0 |
T49 |
192424 |
192195 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49152089 |
19797 |
0 |
0 |
T1 |
3359 |
1 |
0 |
0 |
T2 |
159748 |
62 |
0 |
0 |
T3 |
435821 |
71 |
0 |
0 |
T4 |
21720 |
93 |
0 |
0 |
T7 |
54901 |
131 |
0 |
0 |
T13 |
27822 |
141 |
0 |
0 |
T26 |
14282 |
53 |
0 |
0 |
T27 |
31521 |
46 |
0 |
0 |
T48 |
2492 |
1 |
0 |
0 |
T49 |
192424 |
140 |
0 |
0 |