Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8865028 8863692 0 0
selKnown1 55607877 55606541 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8865028 8863692 0 0
T1 375 373 0 0
T2 14640 14638 0 0
T3 18618 18614 0 0
T4 36686 36682 0 0
T5 0 16 0 0
T6 2 0 0 0
T7 29879 29875 0 0
T8 0 6 0 0
T13 32577 32573 0 0
T26 12505 12501 0 0
T27 10712 10708 0 0
T28 0 4 0 0
T29 0 18 0 0
T31 0 9 0 0
T33 0 22 0 0
T48 444 440 0 0
T49 32267 32263 0 0
T52 0 20 0 0
T57 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 55607877 55606541 0 0
T1 3546 3544 0 0
T2 167068 167066 0 0
T3 445131 445127 0 0
T4 40066 40062 0 0
T5 0 12 0 0
T6 2 0 0 0
T7 69841 69837 0 0
T8 0 6 0 0
T13 44111 44107 0 0
T26 20536 20532 0 0
T27 36878 36874 0 0
T28 0 4 0 0
T29 0 10 0 0
T31 0 4 0 0
T33 0 22 0 0
T48 2715 2711 0 0
T49 208558 208554 0 0
T52 0 20 0 0
T57 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2408781 2408557 0 0
selKnown1 49152089 49151865 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2408781 2408557 0 0
T1 187 186 0 0
T2 7320 7319 0 0
T3 9302 9301 0 0
T4 18338 18337 0 0
T7 14938 14937 0 0
T13 16287 16286 0 0
T26 6250 6249 0 0
T27 5355 5354 0 0
T48 221 220 0 0
T49 16132 16131 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 49152089 49151865 0 0
T1 3359 3358 0 0
T2 159748 159747 0 0
T3 435821 435820 0 0
T4 21720 21719 0 0
T7 54901 54900 0 0
T13 27822 27821 0 0
T26 14282 14281 0 0
T27 31521 31520 0 0
T48 2492 2491 0 0
T49 192424 192423 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 607 383 0 0
selKnown1 583 359 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 607 383 0 0
T3 4 3 0 0
T4 5 4 0 0
T5 0 6 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 0 3 0 0
T13 1 0 0 0
T26 2 1 0 0
T27 1 0 0 0
T28 0 2 0 0
T29 0 5 0 0
T31 0 2 0 0
T33 0 11 0 0
T48 1 0 0 0
T49 1 0 0 0
T52 0 10 0 0
T57 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 583 359 0 0
T3 4 3 0 0
T4 4 3 0 0
T5 0 6 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 0 3 0 0
T13 1 0 0 0
T26 2 1 0 0
T27 1 0 0 0
T28 0 2 0 0
T29 0 5 0 0
T31 0 2 0 0
T33 0 11 0 0
T48 1 0 0 0
T49 1 0 0 0
T52 0 10 0 0
T57 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6453775 6453331 0 0
selKnown1 6453553 6453109 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6453775 6453331 0 0
T1 188 187 0 0
T2 7320 7319 0 0
T3 9303 9302 0 0
T4 18338 18337 0 0
T7 14939 14938 0 0
T13 16288 16287 0 0
T26 6251 6250 0 0
T27 5355 5354 0 0
T48 221 220 0 0
T49 16133 16132 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6453553 6453109 0 0
T1 187 186 0 0
T2 7320 7319 0 0
T3 9302 9301 0 0
T4 18338 18337 0 0
T7 14938 14937 0 0
T13 16287 16286 0 0
T26 6250 6249 0 0
T27 5355 5354 0 0
T48 221 220 0 0
T49 16132 16131 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1865 1421 0 0
selKnown1 1652 1208 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1865 1421 0 0
T3 9 8 0 0
T4 5 4 0 0
T5 0 10 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 0 3 0 0
T13 1 0 0 0
T26 2 1 0 0
T27 1 0 0 0
T28 0 2 0 0
T29 0 13 0 0
T31 0 7 0 0
T33 0 11 0 0
T48 1 0 0 0
T49 1 0 0 0
T52 0 10 0 0
T57 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1652 1208 0 0
T3 4 3 0 0
T4 4 3 0 0
T5 0 6 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 0 3 0 0
T13 1 0 0 0
T26 2 1 0 0
T27 1 0 0 0
T28 0 2 0 0
T29 0 5 0 0
T31 0 2 0 0
T33 0 11 0 0
T48 1 0 0 0
T49 1 0 0 0
T52 0 10 0 0
T57 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%