Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	5687838	1		T2	12		T4	6		T5	8
full_word	1446025	1		T2	3		T4	3		T5	14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7133553	1		T2	15		T4	9		T5	22
auto[TlIntgErrCmd]	111	1		T72	9		T122	6		T128	7
auto[TlIntgErrData]	94	1		T72	5		T122	10		T128	8
auto[TlIntgErrBoth]	105	1		T72	6		T122	4		T128	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	909145	1		T2	6		T4	8		T5	6
auto[1]	6224718	1		T2	9		T4	1		T5	16

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	406054	1		T2	4		T4	5		T5	1
auto[TlIntgErrNone]	partial	auto[1]	5281505	1		T2	8		T4	1		T5	7
auto[TlIntgErrNone]	full_word	auto[0]	502952	1		T2	2		T4	3		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	943042	1		T2	1		T5	9		T6	3
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T72	4		T122	1		T128	4
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T72	4		T122	3		T128	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1		T72	1		T122	1		T157	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T122	1		T128	1		T167	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T72	2		T122	5		T128	3
auto[TlIntgErrData]	partial	auto[1]	34	1		T72	3		T122	5		T128	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T160	1		T124	1		T168	1
auto[TlIntgErrData]	full_word	auto[1]	10	1		T128	2		T160	2		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T72	2		T122	3		T128	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1		T72	3		T122	1		T128	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T158	1		T164	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T72	1		T124	1		T161	1