Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 164386760 1400255 0 0
late_debug_enable_rd_A 164386760 8206 0 0
late_debug_enable_regwen_rd_A 164386760 8563 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 164386760 1400255 0 0
T9 0 58174 0 0
T15 384877 124365 0 0
T19 0 196864 0 0
T21 0 72780 0 0
T24 0 50317 0 0
T27 0 474061 0 0
T50 0 330676 0 0
T53 4010 0 0 0
T67 124431 0 0 0
T70 0 37530 0 0
T71 0 28 0 0
T72 0 7 0 0
T73 2806 0 0 0
T74 2391 0 0 0
T75 51785 0 0 0
T76 13605 0 0 0
T77 4682 0 0 0
T78 3645 0 0 0
T79 2196 0 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 164386760 8206 0 0
T58 128011 268 0 0
T82 60285 35 0 0
T86 9264 8 0 0
T90 20976 38 0 0
T122 98411 57 0 0
T123 7739 58 0 0
T124 104172 87 0 0
T125 15353 34 0 0
T126 8261 14 0 0
T127 11366 53 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 164386760 8563 0 0
T58 128011 260 0 0
T81 337140 1930 0 0
T82 60285 27 0 0
T86 9264 1 0 0
T90 20976 20 0 0
T122 98411 38 0 0
T123 7739 79 0 0
T124 104172 90 0 0
T125 15353 27 0 0
T126 8261 13 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%