Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 27655751 27654407 0 0
selKnown1 105745130 105743786 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 27655751 27654407 0 0
T1 18946 18944 0 0
T2 36480 36476 0 0
T3 8587 8583 0 0
T4 2602 2598 0 0
T5 52868 52864 0 0
T6 0 14 0 0
T7 1788 1784 0 0
T8 0 10 0 0
T13 16 14 0 0
T25 0 8 0 0
T26 0 8 0 0
T39 455 451 0 0
T40 6330 6326 0 0
T41 419 415 0 0
T42 355 351 0 0
T43 0 20 0 0
T48 0 1 0 0
T49 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 105745130 105743786 0 0
T1 74619 74617 0 0
T2 104025 104021 0 0
T3 209438 209434 0 0
T4 19411 19407 0 0
T5 308448 308444 0 0
T6 0 10 0 0
T7 15819 15815 0 0
T8 0 8 0 0
T13 16 14 0 0
T25 0 6 0 0
T26 0 2 0 0
T39 5408 5404 0 0
T40 39580 39576 0 0
T41 3178 3174 0 0
T42 5963 5959 0 0
T43 0 20 0 0
T49 0 6 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 11902352 11902125 0 0
selKnown1 89992350 89992123 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 11902352 11902125 0 0
T1 9473 9472 0 0
T2 18234 18233 0 0
T3 4292 4291 0 0
T4 1300 1299 0 0
T5 26420 26419 0 0
T7 893 892 0 0
T39 226 225 0 0
T40 3144 3143 0 0
T41 208 207 0 0
T42 176 175 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 89992350 89992123 0 0
T1 65146 65145 0 0
T2 85787 85786 0 0
T3 205144 205143 0 0
T4 18109 18108 0 0
T5 282018 282017 0 0
T7 14924 14923 0 0
T39 5180 5179 0 0
T40 36394 36393 0 0
T41 2968 2967 0 0
T42 5785 5784 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 673 446 0 0
selKnown1 613 386 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 673 446 0 0
T2 4 3 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 6 5 0 0
T6 0 7 0 0
T7 1 0 0 0
T8 0 5 0 0
T13 8 7 0 0
T25 0 4 0 0
T26 0 2 0 0
T39 1 0 0 0
T40 21 20 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T49 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 613 386 0 0
T2 2 1 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 5 4 0 0
T6 0 5 0 0
T7 1 0 0 0
T8 0 4 0 0
T13 8 7 0 0
T25 0 3 0 0
T26 0 1 0 0
T39 1 0 0 0
T40 21 20 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T49 0 3 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 15750668 15750223 0 0
selKnown1 15750474 15750029 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 15750668 15750223 0 0
T1 9473 9472 0 0
T2 18235 18234 0 0
T3 4293 4292 0 0
T4 1300 1299 0 0
T5 26420 26419 0 0
T7 893 892 0 0
T39 227 226 0 0
T40 3144 3143 0 0
T41 209 208 0 0
T42 177 176 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 15750474 15750029 0 0
T1 9473 9472 0 0
T2 18234 18233 0 0
T3 4292 4291 0 0
T4 1300 1299 0 0
T5 26420 26419 0 0
T7 893 892 0 0
T39 226 225 0 0
T40 3144 3143 0 0
T41 208 207 0 0
T42 176 175 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2058 1613 0 0
selKnown1 1693 1248 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2058 1613 0 0
T2 7 6 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 22 21 0 0
T6 0 7 0 0
T7 1 0 0 0
T8 0 5 0 0
T13 8 7 0 0
T25 0 4 0 0
T26 0 6 0 0
T39 1 0 0 0
T40 21 20 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T48 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1693 1248 0 0
T2 2 1 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 5 4 0 0
T6 0 5 0 0
T7 1 0 0 0
T8 0 4 0 0
T13 8 7 0 0
T25 0 3 0 0
T26 0 1 0 0
T39 1 0 0 0
T40 21 20 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T49 0 3 0 0

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