Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T1,*T2,*T7 |
Yes |
T2,T7,T4 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T2,T39 |
Yes |
T1,T2,T39 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T2,T7 |
Yes |
T2,T7,T4 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T2,T7,T40 |
Yes |
T2,T40,T41 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T2,T7,T4 |
Yes |
T2,T7,T40 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
158 |
60.77 |
Total Bits 0->1 |
130 |
79 |
60.77 |
Total Bits 1->0 |
130 |
79 |
60.77 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
158 |
60.77 |
Port Bits 0->1 |
130 |
79 |
60.77 |
Port Bits 1->0 |
130 |
79 |
60.77 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[5:0] |
Yes |
Yes |
*T1,*T2,*T7 |
Yes |
T40,T13,T14 |
INPUT |
data_i[56:6] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T2,T40 |
Yes |
T1,T2,T7 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T2,T7 |
Yes |
T40,T13,T14 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T40,T13,T14 |
Yes |
T40,T13,T51 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T2,T40,T13 |
Yes |
T2,T40,T13 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T42,*T6,*T52 |
Yes |
T7,T42,T6 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T2,T39,T7 |
Yes |
T2,T39,T7 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T42,T6,T52 |
Yes |
T7,T42,T6 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T7,T42,T6 |
Yes |
T42,T6,T52 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T7,T42,T6 |
Yes |
T7,T42,T6 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T2,*T4,*T5 |
Yes |
T2,T4,T5 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T41 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T4,T5 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T2,T13,T6 |
Yes |
T2,T41,T13 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T2,T4,T5 |
Yes |
T2,T5,T13 |
OUTPUT |
*Tests covering at least one bit in the range