SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2853935 | 1 | T4 | 2 | T9 | 2 | T5 | 22 | |||
auto[1] | 901644 | 1 | T6 | 80762 | T14 | 200495 | T37 | 25728 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3755386 | 1 | T4 | 2 | T9 | 2 | T5 | 22 | |||
values[1] | 32 | 1 | T82 | 1 | T66 | 4 | T67 | 1 | |||
values[2] | 6 | 1 | T64 | 2 | T150 | 1 | T151 | 2 | |||
values[3] | 97 | 1 | T64 | 3 | T65 | 5 | T82 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3755383 | 1 | T4 | 2 | T9 | 2 | T5 | 22 | |||
values[1] | 22 | 1 | T64 | 3 | T65 | 1 | T82 | 1 | |||
values[2] | 6 | 1 | T82 | 1 | T152 | 2 | T150 | 1 | |||
values[3] | 107 | 1 | T64 | 6 | T65 | 3 | T82 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3755289 | 1 | T4 | 2 | T9 | 2 | T5 | 22 | |||
auto[TlIntgErrCmd] | 94 | 1 | T64 | 9 | T65 | 4 | T82 | 4 | |||
auto[TlIntgErrData] | 97 | 1 | T64 | 6 | T65 | 3 | T82 | 5 | |||
auto[TlIntgErrBoth] | 99 | 1 | T64 | 5 | T65 | 3 | T82 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 1386369 | 0 | T1 | 1 | T2 | 4 | T8 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1386168 | 1 | T1 | 1 | T2 | 4 | T8 | 1 | |||
values[1] | 17 | 1 | T64 | 2 | T65 | 1 | T66 | 1 | |||
values[2] | 6 | 1 | T153 | 1 | T154 | 1 | T155 | 1 | |||
values[3] | 101 | 1 | T64 | 8 | T65 | 2 | T82 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1386176 | 1 | T1 | 1 | T2 | 4 | T8 | 1 | |||
values[1] | 23 | 1 | T64 | 1 | T82 | 1 | T66 | 4 | |||
values[2] | 5 | 1 | T65 | 1 | T153 | 1 | T155 | 1 | |||
values[3] | 78 | 1 | T64 | 6 | T65 | 3 | T82 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1386079 | 1 | T1 | 1 | T2 | 4 | T8 | 1 | |||
auto[TlIntgErrCmd] | 97 | 1 | T64 | 5 | T65 | 2 | T82 | 4 | |||
auto[TlIntgErrData] | 89 | 1 | T64 | 7 | T65 | 4 | T82 | 2 | |||
auto[TlIntgErrBoth] | 104 | 1 | T64 | 8 | T65 | 4 | T82 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |