Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
2794442 |
1 |
|
T4 |
1 |
|
T5 |
14 |
|
T6 |
231610 |
full_word |
961137 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T5 |
8 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
3755289 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T5 |
22 |
auto[TlIntgErrCmd] |
94 |
1 |
|
T64 |
9 |
|
T65 |
4 |
|
T82 |
4 |
auto[TlIntgErrData] |
97 |
1 |
|
T64 |
6 |
|
T65 |
3 |
|
T82 |
5 |
auto[TlIntgErrBoth] |
99 |
1 |
|
T64 |
5 |
|
T65 |
3 |
|
T82 |
1 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
663777 |
1 |
|
T5 |
8 |
|
T6 |
17887 |
|
T7 |
7 |
auto[1] |
3091802 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T5 |
14 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
288584 |
1 |
|
T5 |
4 |
|
T6 |
8671 |
|
T7 |
1 |
auto[TlIntgErrNone] |
partial |
auto[1] |
2505588 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T6 |
222939 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
375052 |
1 |
|
T5 |
4 |
|
T6 |
9216 |
|
T7 |
6 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
586065 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T5 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
39 |
1 |
|
T64 |
2 |
|
T65 |
2 |
|
T82 |
3 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
48 |
1 |
|
T64 |
5 |
|
T65 |
2 |
|
T82 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T156 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
T64 |
1 |
|
T156 |
1 |
|
T157 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
55 |
1 |
|
T64 |
3 |
|
T65 |
2 |
|
T82 |
5 |
auto[TlIntgErrData] |
partial |
auto[1] |
39 |
1 |
|
T64 |
2 |
|
T65 |
1 |
|
T66 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
2 |
1 |
|
T66 |
1 |
|
T154 |
1 |
|
- |
- |
auto[TlIntgErrData] |
full_word |
auto[1] |
1 |
1 |
|
T64 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrBoth] |
partial |
auto[0] |
38 |
1 |
|
T64 |
2 |
|
T65 |
2 |
|
T66 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
51 |
1 |
|
T64 |
2 |
|
T65 |
1 |
|
T82 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
4 |
1 |
|
T157 |
1 |
|
T158 |
1 |
|
T151 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
6 |
1 |
|
T64 |
1 |
|
T157 |
2 |
|
T158 |
2 |