Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
179144764 |
656677 |
0 |
0 |
T6 |
332070 |
62190 |
0 |
0 |
T7 |
482960 |
0 |
0 |
0 |
T11 |
0 |
110276 |
0 |
0 |
T12 |
0 |
141304 |
0 |
0 |
T14 |
0 |
148167 |
0 |
0 |
T18 |
0 |
50694 |
0 |
0 |
T23 |
213787 |
0 |
0 |
0 |
T28 |
38129 |
0 |
0 |
0 |
T32 |
95393 |
0 |
0 |
0 |
T37 |
0 |
19623 |
0 |
0 |
T42 |
1822 |
0 |
0 |
0 |
T43 |
17173 |
0 |
0 |
0 |
T44 |
49474 |
0 |
0 |
0 |
T47 |
1356 |
0 |
0 |
0 |
T48 |
3431 |
0 |
0 |
0 |
T63 |
0 |
52109 |
0 |
0 |
T64 |
0 |
9 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
T66 |
0 |
7 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
179144764 |
87157 |
0 |
0 |
T11 |
554429 |
37032 |
0 |
0 |
T12 |
0 |
48011 |
0 |
0 |
T45 |
5069 |
0 |
0 |
0 |
T64 |
0 |
45 |
0 |
0 |
T65 |
0 |
32 |
0 |
0 |
T74 |
0 |
7 |
0 |
0 |
T75 |
0 |
7 |
0 |
0 |
T78 |
0 |
10 |
0 |
0 |
T82 |
0 |
36 |
0 |
0 |
T89 |
0 |
7 |
0 |
0 |
T113 |
0 |
26 |
0 |
0 |
T114 |
500925 |
0 |
0 |
0 |
T115 |
2881 |
0 |
0 |
0 |
T116 |
488448 |
0 |
0 |
0 |
T117 |
262360 |
0 |
0 |
0 |
T118 |
14187 |
0 |
0 |
0 |
T119 |
1761 |
0 |
0 |
0 |
T120 |
2202 |
0 |
0 |
0 |
T121 |
71707 |
0 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
179144764 |
76269 |
0 |
0 |
T11 |
554429 |
32255 |
0 |
0 |
T12 |
0 |
41993 |
0 |
0 |
T45 |
5069 |
0 |
0 |
0 |
T64 |
0 |
40 |
0 |
0 |
T65 |
0 |
47 |
0 |
0 |
T74 |
0 |
4 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T77 |
0 |
2 |
0 |
0 |
T78 |
0 |
4 |
0 |
0 |
T82 |
0 |
39 |
0 |
0 |
T113 |
0 |
48 |
0 |
0 |
T114 |
500925 |
0 |
0 |
0 |
T115 |
2881 |
0 |
0 |
0 |
T116 |
488448 |
0 |
0 |
0 |
T117 |
262360 |
0 |
0 |
0 |
T118 |
14187 |
0 |
0 |
0 |
T119 |
1761 |
0 |
0 |
0 |
T120 |
2202 |
0 |
0 |
0 |
T121 |
71707 |
0 |
0 |
0 |