SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 224 | 224 | 0 | 0 |
OutputsKnown_A | 81199098 | 81156537 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 81199098 | 81154797 | 0 | 672 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 224 | 224 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 81199098 | 81156537 | 0 | 0 |
T1 | 20462 | 20402 | 0 | 0 |
T2 | 4188 | 4124 | 0 | 0 |
T3 | 249261 | 249195 | 0 | 0 |
T4 | 37521 | 37464 | 0 | 0 |
T5 | 324058 | 323649 | 0 | 0 |
T8 | 269075 | 269001 | 0 | 0 |
T9 | 5153 | 5072 | 0 | 0 |
T22 | 77208 | 77141 | 0 | 0 |
T35 | 624066 | 623996 | 0 | 0 |
T36 | 30978 | 29593 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 81199098 | 81154797 | 0 | 672 |
T1 | 20462 | 20399 | 0 | 3 |
T2 | 4188 | 4121 | 0 | 3 |
T3 | 249261 | 249192 | 0 | 3 |
T4 | 37521 | 37461 | 0 | 3 |
T5 | 324058 | 323628 | 0 | 3 |
T8 | 269075 | 268998 | 0 | 3 |
T9 | 5153 | 5069 | 0 | 3 |
T22 | 77208 | 77138 | 0 | 3 |
T35 | 624066 | 623993 | 0 | 3 |
T36 | 30978 | 29530 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |