Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
81199098 |
81156537 |
0 |
0 |
T1 |
20462 |
20402 |
0 |
0 |
T2 |
4188 |
4124 |
0 |
0 |
T3 |
249261 |
249195 |
0 |
0 |
T4 |
37521 |
37464 |
0 |
0 |
T5 |
324058 |
323649 |
0 |
0 |
T8 |
269075 |
269001 |
0 |
0 |
T9 |
5153 |
5072 |
0 |
0 |
T22 |
77208 |
77141 |
0 |
0 |
T35 |
624066 |
623996 |
0 |
0 |
T36 |
30978 |
29593 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
81199098 |
81156537 |
0 |
0 |
T1 |
20462 |
20402 |
0 |
0 |
T2 |
4188 |
4124 |
0 |
0 |
T3 |
249261 |
249195 |
0 |
0 |
T4 |
37521 |
37464 |
0 |
0 |
T5 |
324058 |
323649 |
0 |
0 |
T8 |
269075 |
269001 |
0 |
0 |
T9 |
5153 |
5072 |
0 |
0 |
T22 |
77208 |
77141 |
0 |
0 |
T35 |
624066 |
623996 |
0 |
0 |
T36 |
30978 |
29593 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
81199098 |
81156537 |
0 |
0 |
T1 |
20462 |
20402 |
0 |
0 |
T2 |
4188 |
4124 |
0 |
0 |
T3 |
249261 |
249195 |
0 |
0 |
T4 |
37521 |
37464 |
0 |
0 |
T5 |
324058 |
323649 |
0 |
0 |
T8 |
269075 |
269001 |
0 |
0 |
T9 |
5153 |
5072 |
0 |
0 |
T22 |
77208 |
77141 |
0 |
0 |
T35 |
624066 |
623996 |
0 |
0 |
T36 |
30978 |
29593 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
81199098 |
81156537 |
0 |
0 |
T1 |
20462 |
20402 |
0 |
0 |
T2 |
4188 |
4124 |
0 |
0 |
T3 |
249261 |
249195 |
0 |
0 |
T4 |
37521 |
37464 |
0 |
0 |
T5 |
324058 |
323649 |
0 |
0 |
T8 |
269075 |
269001 |
0 |
0 |
T9 |
5153 |
5072 |
0 |
0 |
T22 |
77208 |
77141 |
0 |
0 |
T35 |
624066 |
623996 |
0 |
0 |
T36 |
30978 |
29593 |
0 |
0 |