Line Coverage for Module :
prim_fifo_async_simple
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
CONT_ASSIGN | 40 | 1 | 1 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 51 | 5 | 5 | 100.00 |
ALWAYS | 85 | 2 | 2 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
43 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_async_simple
| Total | Covered | Percent |
Conditions | 16 | 14 | 87.50 |
Logical | 16 | 14 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 39
EXPRESSION (((!pending_q)) && not_in_reset_q)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
LINE 40
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T8 |
LINE 41
EXPRESSION (pending_q || wvalid_i)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Covered | T1,T2,T8 |
LINE 43
EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T8 |
1 | Covered | T1,T2,T8 |
LINE 43
SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T8 |
1 | Covered | T1,T2,T8 |
LINE 48
EXPRESSION (dst_req && rready_i)
---1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T8 |
Branch Coverage for Module :
prim_fifo_async_simple
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
43 |
3 |
3 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
85 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 43 (src_ack) ?
-2-: 43 (wr_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T8 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
Covered |
T1,T2,T8 |
LineNo. Expression
-1-: 51 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T8 |
0 |
Covered |
T1,T2,T8 |
LineNo. Expression
-1-: 85 if (wr_en)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T8 |
0 |
Covered |
T1,T2,T8 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
CONT_ASSIGN | 40 | 1 | 1 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 51 | 5 | 5 | 100.00 |
ALWAYS | 85 | 2 | 2 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
43 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req
| Total | Covered | Percent |
Conditions | 16 | 14 | 87.50 |
Logical | 16 | 14 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 39
EXPRESSION (((!pending_q)) && not_in_reset_q)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
LINE 40
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T8 |
LINE 41
EXPRESSION (pending_q || wvalid_i)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Covered | T1,T2,T8 |
LINE 43
EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T8 |
1 | Covered | T1,T2,T8 |
LINE 43
SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T8 |
1 | Covered | T1,T2,T8 |
LINE 48
EXPRESSION (dst_req && rready_i)
---1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T8 |
Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
43 |
3 |
3 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
85 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 43 (src_ack) ?
-2-: 43 (wr_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T8 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
Covered |
T1,T2,T8 |
LineNo. Expression
-1-: 51 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T8 |
0 |
Covered |
T1,T2,T8 |
LineNo. Expression
-1-: 85 if (wr_en)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T8 |
0 |
Covered |
T1,T2,T8 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
CONT_ASSIGN | 40 | 1 | 1 | 100.00 |
CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 51 | 5 | 5 | 100.00 |
ALWAYS | 85 | 2 | 2 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
43 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp
| Total | Covered | Percent |
Conditions | 15 | 14 | 93.33 |
Logical | 15 | 14 | 93.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 39
EXPRESSION (((!pending_q)) && not_in_reset_q)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
LINE 40
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T8 |
LINE 41
EXPRESSION (pending_q || wvalid_i)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Covered | T1,T2,T8 |
LINE 43
EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T8 |
1 | Covered | T1,T2,T8 |
LINE 43
SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T8 |
1 | Covered | T1,T2,T8 |
LINE 48
EXPRESSION (dst_req && rready_i)
---1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Unreachable | |
1 | 1 | Covered | T1,T2,T8 |
Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
43 |
3 |
3 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
85 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 43 (src_ack) ?
-2-: 43 (wr_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T8 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
Covered |
T1,T2,T8 |
LineNo. Expression
-1-: 51 if ((!rst_wr_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T8 |
0 |
Covered |
T1,T2,T8 |
LineNo. Expression
-1-: 85 if (wr_en)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T8 |
0 |
Covered |
T1,T2,T8 |