Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
17150214 |
17148880 |
0 |
0 |
selKnown1 |
91766335 |
91765001 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17150214 |
17148880 |
0 |
0 |
T1 |
13987 |
13985 |
0 |
0 |
T2 |
346 |
344 |
0 |
0 |
T3 |
35696 |
35694 |
0 |
0 |
T4 |
1998 |
1996 |
0 |
0 |
T5 |
26850 |
26846 |
0 |
0 |
T6 |
15 |
13 |
0 |
0 |
T7 |
0 |
12 |
0 |
0 |
T8 |
11736 |
11734 |
0 |
0 |
T9 |
1039 |
1035 |
0 |
0 |
T22 |
10559 |
10557 |
0 |
0 |
T23 |
0 |
14 |
0 |
0 |
T25 |
2 |
0 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T28 |
2 |
0 |
0 |
0 |
T31 |
0 |
6 |
0 |
0 |
T35 |
24500 |
24498 |
0 |
0 |
T36 |
6840 |
6836 |
0 |
0 |
T41 |
2 |
0 |
0 |
0 |
T42 |
2 |
0 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
0 |
40 |
0 |
0 |
T46 |
0 |
20 |
0 |
0 |
T47 |
2 |
0 |
0 |
0 |
T48 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91766335 |
91765001 |
0 |
0 |
T1 |
27455 |
27453 |
0 |
0 |
T2 |
4361 |
4359 |
0 |
0 |
T3 |
267109 |
267107 |
0 |
0 |
T4 |
38520 |
38518 |
0 |
0 |
T5 |
337489 |
337485 |
0 |
0 |
T6 |
12 |
10 |
0 |
0 |
T7 |
0 |
8 |
0 |
0 |
T8 |
274943 |
274941 |
0 |
0 |
T9 |
5673 |
5669 |
0 |
0 |
T22 |
82487 |
82485 |
0 |
0 |
T23 |
0 |
14 |
0 |
0 |
T25 |
2 |
0 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T28 |
2 |
0 |
0 |
0 |
T31 |
0 |
6 |
0 |
0 |
T35 |
636316 |
636314 |
0 |
0 |
T36 |
34419 |
34415 |
0 |
0 |
T41 |
2 |
0 |
0 |
0 |
T42 |
2 |
0 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
0 |
40 |
0 |
0 |
T46 |
0 |
20 |
0 |
0 |
T47 |
2 |
0 |
0 |
0 |
T48 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6582337 |
6582113 |
0 |
0 |
selKnown1 |
81199098 |
81198874 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6582337 |
6582113 |
0 |
0 |
T1 |
6993 |
6992 |
0 |
0 |
T2 |
173 |
172 |
0 |
0 |
T3 |
17848 |
17847 |
0 |
0 |
T4 |
999 |
998 |
0 |
0 |
T5 |
13417 |
13416 |
0 |
0 |
T8 |
5868 |
5867 |
0 |
0 |
T9 |
518 |
517 |
0 |
0 |
T22 |
5279 |
5278 |
0 |
0 |
T35 |
12250 |
12249 |
0 |
0 |
T36 |
3399 |
3398 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
81199098 |
81198874 |
0 |
0 |
T1 |
20462 |
20461 |
0 |
0 |
T2 |
4188 |
4187 |
0 |
0 |
T3 |
249261 |
249260 |
0 |
0 |
T4 |
37521 |
37520 |
0 |
0 |
T5 |
324058 |
324057 |
0 |
0 |
T8 |
269075 |
269074 |
0 |
0 |
T9 |
5153 |
5152 |
0 |
0 |
T22 |
77208 |
77207 |
0 |
0 |
T35 |
624066 |
624065 |
0 |
0 |
T36 |
30978 |
30977 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
632 |
408 |
0 |
0 |
T5 |
8 |
7 |
0 |
0 |
T6 |
8 |
7 |
0 |
0 |
T7 |
0 |
6 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
21 |
20 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
580 |
356 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
21 |
20 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10565206 |
10564763 |
0 |
0 |
selKnown1 |
10565008 |
10564565 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10565206 |
10564763 |
0 |
0 |
T1 |
6994 |
6993 |
0 |
0 |
T2 |
173 |
172 |
0 |
0 |
T3 |
17848 |
17847 |
0 |
0 |
T4 |
999 |
998 |
0 |
0 |
T5 |
13417 |
13416 |
0 |
0 |
T8 |
5868 |
5867 |
0 |
0 |
T9 |
519 |
518 |
0 |
0 |
T22 |
5280 |
5279 |
0 |
0 |
T35 |
12250 |
12249 |
0 |
0 |
T36 |
3399 |
3398 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10565008 |
10564565 |
0 |
0 |
T1 |
6993 |
6992 |
0 |
0 |
T2 |
173 |
172 |
0 |
0 |
T3 |
17848 |
17847 |
0 |
0 |
T4 |
999 |
998 |
0 |
0 |
T5 |
13417 |
13416 |
0 |
0 |
T8 |
5868 |
5867 |
0 |
0 |
T9 |
518 |
517 |
0 |
0 |
T22 |
5279 |
5278 |
0 |
0 |
T35 |
12250 |
12249 |
0 |
0 |
T36 |
3399 |
3398 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T8 |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2039 |
1596 |
0 |
0 |
selKnown1 |
1649 |
1206 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2039 |
1596 |
0 |
0 |
T5 |
8 |
7 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
0 |
6 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
21 |
20 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1649 |
1206 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
6 |
5 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T31 |
0 |
3 |
0 |
0 |
T36 |
21 |
20 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T42 |
1 |
0 |
0 |
0 |
T43 |
0 |
10 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |