Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144412885 |
894289 |
0 |
0 |
T5 |
319460 |
58684 |
0 |
0 |
T6 |
0 |
140031 |
0 |
0 |
T9 |
0 |
128601 |
0 |
0 |
T10 |
0 |
105280 |
0 |
0 |
T11 |
471125 |
0 |
0 |
0 |
T12 |
384554 |
0 |
0 |
0 |
T17 |
305637 |
0 |
0 |
0 |
T18 |
31347 |
0 |
0 |
0 |
T20 |
141346 |
0 |
0 |
0 |
T21 |
127380 |
0 |
0 |
0 |
T24 |
2147 |
0 |
0 |
0 |
T27 |
281195 |
0 |
0 |
0 |
T35 |
0 |
124219 |
0 |
0 |
T36 |
206778 |
0 |
0 |
0 |
T72 |
0 |
105982 |
0 |
0 |
T73 |
0 |
146177 |
0 |
0 |
T74 |
0 |
30831 |
0 |
0 |
T75 |
0 |
1 |
0 |
0 |
T76 |
0 |
654 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144412885 |
15749 |
0 |
0 |
T49 |
0 |
492 |
0 |
0 |
T74 |
170855 |
10543 |
0 |
0 |
T77 |
0 |
89 |
0 |
0 |
T81 |
0 |
6 |
0 |
0 |
T87 |
0 |
3 |
0 |
0 |
T94 |
0 |
3 |
0 |
0 |
T112 |
0 |
85 |
0 |
0 |
T113 |
0 |
45 |
0 |
0 |
T114 |
0 |
153 |
0 |
0 |
T115 |
0 |
92 |
0 |
0 |
T116 |
3804 |
0 |
0 |
0 |
T117 |
3631 |
0 |
0 |
0 |
T118 |
114094 |
0 |
0 |
0 |
T119 |
3580 |
0 |
0 |
0 |
T120 |
3755 |
0 |
0 |
0 |
T121 |
17868 |
0 |
0 |
0 |
T122 |
120301 |
0 |
0 |
0 |
T123 |
28173 |
0 |
0 |
0 |
T124 |
113339 |
0 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
144412885 |
13797 |
0 |
0 |
T49 |
0 |
414 |
0 |
0 |
T74 |
170855 |
9149 |
0 |
0 |
T77 |
0 |
84 |
0 |
0 |
T81 |
0 |
1 |
0 |
0 |
T87 |
0 |
9 |
0 |
0 |
T94 |
0 |
13 |
0 |
0 |
T112 |
0 |
71 |
0 |
0 |
T113 |
0 |
38 |
0 |
0 |
T114 |
0 |
129 |
0 |
0 |
T115 |
0 |
94 |
0 |
0 |
T116 |
3804 |
0 |
0 |
0 |
T117 |
3631 |
0 |
0 |
0 |
T118 |
114094 |
0 |
0 |
0 |
T119 |
3580 |
0 |
0 |
0 |
T120 |
3755 |
0 |
0 |
0 |
T121 |
17868 |
0 |
0 |
0 |
T122 |
120301 |
0 |
0 |
0 |
T123 |
28173 |
0 |
0 |
0 |
T124 |
113339 |
0 |
0 |
0 |