Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.35	100.00	76.60	92.63		100.00	87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.35	100.00	76.60	92.63		100.00	87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.35	100.00	76.60	92.63		100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.43	96.18	85.48	89.91	72.50	88.33	98.21

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	84.25	98.36	86.58		67.31	94.02	75.00
enable_checker	100.00	100.00					100.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	97.10	99.00	96.63	93.33		96.55	100.00
rv_dm_regs_csr_assert	100.00						100.00
tl_adapter_host_sba	95.14	100.00	100.00	75.71		100.00	100.00
tlul_assert_device_mem	100.00	100.00				100.00	100.00
tlul_assert_device_regs	99.65	100.00				100.00	98.95
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	86.58	89.68	72.77		92.86	77.58	100.00
u_lc_en_sync_copies	100.00	100.00					100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_flop_2sync_lc_rst_assert	100.00	100.00				100.00
u_prim_flop_2sync_lc_rst_sync	100.00	100.00				100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_mubi32_sync_late_debug_enable	100.00	100.00					100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug	100.00	100.00				100.00	100.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg_regs	98.19	98.69	98.71	93.55		100.00	100.00
u_tlul_lc_gate_rom	92.59	100.00	92.86		85.71	96.88	87.50
u_tlul_lc_gate_sba	79.08	94.49	75.00		57.14	81.25	87.50

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		33	33	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	551	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
128	1	1
131	1	1
154	1	1
236	1	1
237	1	1
239	4	4
278	1	1
288	1	1
289	1	1
320	1	1
321	1	1
322	1	1
325	1	1
326	1	1
327	1	1
328	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
334	1	1
			MISSING_ELSE
345	1	1
432	1	1
438	1	1
440	1	1
446	1	1
447	1	1
523	1	1
551	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	47	36	76.60
Logical	47	36	76.60
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T42,T43,T44

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T54,T55
1	0	Covered	T1,T4,T5
1	1	Covered	T24,T40,T41

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T21
1	1	Covered	T1,T4,T5

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T4,T5,T21

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T5,T21

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T5,T21

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Not Covered
1	0	1	1	1	Covered	T1,T4,T5
1	1	0	1	1	Not Covered
1	1	1	0	1	Covered	T4,T5,T21
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T4,T5,T21

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T56
1	1	Covered	T1,T3,T4

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	98	80	81.63
Total Bits	1140	1056	92.63
Total Bits 0->1	570	528	92.63
Total Bits 1->0	570	528	92.63

Ports	98	80	81.63
Port Bits	1140	1056	92.63
Port Bits 0->1	570	528	92.63
Port Bits 1->0	570	528	92.63

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
lc_dft_en_i[3:0]	No	No		No		INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T3,T5,T30	Yes	T3,T5,T30	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
scanmode_i[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T3,T4	INPUT
scan_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
dmactive_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
unavailable_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T5	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T11	Yes	T1,T5,T11	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T1,T11,T17	Yes	T1,T11,T17	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T5,T11	Yes	T1,T5,T11	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T1,T5,T11	Yes	T1,T5,T11	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T1,T5,T11	Yes	T1,T5,T11	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T1,T11,T17	Yes	T1,T11,T17	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T5,T40,T6	Yes	T5,T40,T6	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T9	Yes	T5,T6,T9	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T3,T5,T18	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T5,T18,T17	Yes	T5,T18,T17	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T17,T27,T30	Yes	T18,T17,T27	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T5,T18,T21	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T1,T5,T18	Yes	T1,T5,T18	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T5,T18,T21	Yes	T1,T5,T18	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T4	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T18,T17,T27	Yes	T18,T17,T27	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T5	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T5,T21	Yes	T1,T5,T21	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T4	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T2,*T11,*T12	Yes	T2,T11,T12	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T2,T11,T36	Yes	T2,T11,T36	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T2,T36,T27	Yes	T2,T36,T27	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T2,T11,T36	Yes	T2,T11,T36	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T2,T27,T30	Yes	T2,T36,T27	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T24,T40,T41	Yes	T24,T40,T41	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T24,T40,T41	Yes	T24,T40,T41	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	320	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	325	if ((ndmreset_req && (!ndmreset_pending_q)))
-3-:	327	if ((ndmreset_ack && ndmreset_pending_q))
-4-:	331	if ((ndmreset_pending_q && lc_rst_asserted))
-5-:	333	if ((ndmreset_ack && lc_rst_pending_q))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T4,T5
0	0	1	-	-	Covered	T4,T5,T21
0	0	0	-	-	Covered	T1,T2,T3
0	-	-	1	-	Covered	T4,T5,T21
0	-	-	0	1	Covered	T4,T5,T21
0	-	-	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	92217237	92165992	0	0
DmactiveOKnown_A	92217237	92165992	0	0
FpvSecCmRegWeOnehotCheck_A	92217237	80	0	0
FpvSecCmRomTlLcGateFsm_A	92217237	0	0	0
FpvSecCmSbaTlLcGateFsm_A	92217237	0	0	0
JtagRspOTdoKnown_A	9143806	9143640	0	0
JtagRspOTdoOeKnown_A	9143806	9143640	0	0
NdmresetOKnown_A	92217237	92165992	0	0
RvDmLcEnDebugVal_A	92217237	92165992	0	0
TlMemAReadyKnown_A	92217237	92165992	0	0
TlMemDValidKnown_A	92217237	92165992	0	0
TlRegsAReadyKnown_A	92217237	92165992	0	0
TlRegsDValidKnown_A	92217237	92165992	0	0
TlSbaAValidKnown_A	92217237	92165992	0	0
TlSbaDReadyKnown_A	92217237	92165992	0	0
paramCheckNrHarts	246	246	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	80	0	0
T13	433960	0	0	0
T34	421627	0	0	0
T37	3916	0	0	0
T42	117200	10	0	0
T43	0	20	0	0
T44	0	10	0	0
T50	47437	0	0	0
T57	0	20	0	0
T58	0	20	0	0
T59	109193	0	0	0
T60	3886	0	0	0
T61	3409	0	0	0
T62	18767	0	0	0
T63	103595	0	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9143806	9143640	0	0
T1	14502	14501	0	0
T2	155506	155506	0	0
T3	6254	6253	0	0
T4	11797	11796	0	0
T5	404698	404695	0	0
T11	17969	17969	0	0
T12	10526	10526	0	0
T18	1627	1627	0	0
T21	15926	15925	0	0
T24	215	215	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9143806	9143640	0	0
T1	14502	14501	0	0
T2	155506	155506	0	0
T3	6254	6253	0	0
T4	11797	11796	0	0
T5	404698	404695	0	0
T11	17969	17969	0	0
T12	10526	10526	0	0
T18	1627	1627	0	0
T21	15926	15925	0	0
T24	215	215	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92217237	92165992	0	0
T1	345573	345209	0	0
T2	281664	281601	0	0
T3	141257	140899	0	0
T4	221143	220964	0	0
T5	319460	319422	0	0
T11	471125	470842	0	0
T12	384554	384477	0	0
T18	31347	31294	0	0
T21	127380	127178	0	0
T24	2147	2096	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	246	246	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0