Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.09 100.00 85.71 97.23 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 87363107 74296 0 0
late_debug_enable_rd_A 87363107 4806 0 0
late_debug_enable_regwen_rd_A 87363107 4369 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 87363107 74296 0 0
T4 178928 3083 0 0
T5 315533 0 0 0
T16 0 15912 0 0
T17 4180 0 0 0
T23 0 4120 0 0
T28 101818 0 0 0
T29 22230 0 0 0
T33 4727 0 0 0
T34 16459 0 0 0
T35 17481 0 0 0
T41 0 14832 0 0
T43 0 3402 0 0
T51 1350 0 0 0
T84 0 4884 0 0
T93 7439 0 0 0
T103 0 5972 0 0
T104 0 1 0 0
T105 0 707 0 0
T106 0 163 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 87363107 4806 0 0
T4 178928 1231 0 0
T5 315533 0 0 0
T17 4180 0 0 0
T28 101818 0 0 0
T29 22230 0 0 0
T33 4727 0 0 0
T34 16459 0 0 0
T35 17481 0 0 0
T43 0 1124 0 0
T51 1350 0 0 0
T93 7439 0 0 0
T105 0 252 0 0
T107 0 293 0 0
T118 0 53 0 0
T121 0 7 0 0
T139 0 22 0 0
T140 0 56 0 0
T141 0 18 0 0
T142 0 3 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 87363107 4369 0 0
T4 178928 1046 0 0
T5 315533 0 0 0
T17 4180 0 0 0
T28 101818 0 0 0
T29 22230 0 0 0
T33 4727 0 0 0
T34 16459 0 0 0
T35 17481 0 0 0
T43 0 1257 0 0
T51 1350 0 0 0
T93 7439 0 0 0
T105 0 170 0 0
T107 0 265 0 0
T118 0 21 0 0
T121 0 6 0 0
T139 0 14 0 0
T140 0 23 0 0
T141 0 10 0 0
T142 0 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%