Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.28	100.00	76.60	92.28		100.00	87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.09	100.00	85.71	97.23		100.00	87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.09	100.00	85.71	97.23		100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.59	96.02	86.85	91.55	75.64	89.08	98.42

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	85.00	98.36	86.58		70.00	95.05	75.00
enable_checker	100.00	100.00					100.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	97.55	99.00	98.86	93.33		96.55	100.00
rv_dm_regs_csr_assert	100.00						100.00
tl_adapter_host_sba	85.80	97.67	77.78	73.57		80.00	100.00
tlul_assert_device_mem	100.00	100.00				100.00	100.00
tlul_assert_device_regs	99.88	100.00				100.00	99.65
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	86.70	89.29	73.80		92.86	77.57	100.00
u_lc_en_sync_copies	100.00	100.00					100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_flop_2sync_lc_rst_assert	100.00	100.00				100.00
u_prim_flop_2sync_lc_rst_sync	100.00	100.00				100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_mubi32_sync_late_debug_enable	100.00	100.00					100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug	100.00	100.00				100.00	100.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg_regs	98.32	98.69	99.35	93.55		100.00	100.00
u_tlul_lc_gate_rom	97.50	100.00	100.00		100.00	100.00	87.50
u_tlul_lc_gate_sba	81.96	94.49	84.00		57.14	86.67	87.50

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		33	33	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	551	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
128	1	1
131	1	1
154	1	1
236	1	1
237	1	1
239	4	4
278	1	1
288	1	1
289	1	1
320	1	1
321	1	1
322	1	1
325	1	1
326	1	1
327	1	1
328	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
334	1	1
			MISSING_ELSE
345	1	1
432	1	1
438	1	1
440	1	1
446	1	1
447	1	1
523	1	1
551	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	47	36	76.60
Logical	47	36	76.60
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T52,T53

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T35
1	0	Covered	T2,T3,T32
1	1	Covered	T32,T35,T51

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T28
1	1	Covered	T2,T3,T28

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T28
1	1	Covered	T2,T3,T28

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T28
1	0	Not Covered
1	1	Covered	T2,T3,T28

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T32,T4
1	0	Covered	T2,T3,T28
1	1	Covered	T2,T3,T28

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T28

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Not Covered
1	0	1	1	1	Covered	T2,T5,T58
1	1	0	1	1	Not Covered
1	1	1	0	1	Covered	T2,T3,T28
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T2,T3,T28

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T11,T13
1	1	Covered	T2,T3,T4

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	98	79	80.61
Total Bits	1140	1052	92.28
Total Bits 0->1	570	526	92.28
Total Bits 1->0	570	526	92.28

Ports	98	79	80.61
Port Bits	1140	1052	92.28
Port Bits 0->1	570	526	92.28
Port Bits 1->0	570	526	92.28

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T34	INPUT
lc_dft_en_i[3:0]	No	No		No		INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T5,T45,T14	Yes	T5,T45,T14	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T2,T3,T24	Yes	T2,T3,T4	INPUT
scanmode_i[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
scan_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T2,T3,T28	Yes	T2,T3,T28	OUTPUT
dmactive_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T2,T4,T28	Yes	T2,T3,T4	OUTPUT
unavailable_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T32,T4,T82	Yes	T32,T4,T82	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T32,T82,T11	Yes	T32,T82,T83	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T32,T4,T82	Yes	T32,T4,T82	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T32,T4,T82	Yes	T32,T4,T82	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T32,T4,T28	Yes	T32,T4,T28	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T32,T4,T33	Yes	T32,T4,T35	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T32,T82,T83	Yes	T32,T82,T20	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T4,T43,T23	Yes	T4,T43,T23	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T43,T23	Yes	T4,T43,T23	OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,T4	Yes	T2,T3,T32	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T32	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T4,T28,T33	Yes	T4,T28,T33	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T32,T4,T33	Yes	T32,T4,T33	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T43,*T23	Yes	T4,T43,T23	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T28	Yes	T2,T3,T4	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T29	Yes	T2,T4,T17	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T2,T17,T29	Yes	T2,T17,T29	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T2,T17,T29	Yes	T2,T29,T58	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T28,T29	Yes	T4,T28,T29	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	T2,*T3,T4	Yes	T2,T3,T4	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T4,T28,T29	Yes	T2,T4,T28	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T71	Yes	T59,T60,T71	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T13,T60,T71	Yes	T13,T60,T71	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T88,T78,T89	Yes	T90,T88,T91	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T60,*T92,*T89	Yes	T60,T92,T89	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T13,T59,T71	Yes	T13,T59,T71	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T2,T5,T14	Yes	T3,T35,T93	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T32	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T34,T5	Yes	T2,T3,T5	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T3,T14,T65	Yes	T2,T3,T32	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T2,T3,T5	Yes	T2,T3,T32	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T14	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T5	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T14	INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T5	Yes	T3,T35,T5	INPUT
sba_tl_h_i.d_opcode[2:1]	No	No		No		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T13,T59,T71	Yes	T13,T59,T71	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T32,T35	Yes	T1,T32,T35	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T32,T35	Yes	T1,T32,T35	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	320	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	325	if ((ndmreset_req && (!ndmreset_pending_q)))
-3-:	327	if ((ndmreset_ack && ndmreset_pending_q))
-4-:	331	if ((ndmreset_pending_q && lc_rst_asserted))
-5-:	333	if ((ndmreset_ack && lc_rst_pending_q))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T28
0	0	1	-	-	Covered	T2,T3,T28
0	0	0	-	-	Covered	T1,T2,T3
0	-	-	1	-	Covered	T2,T3,T28
0	-	-	0	1	Covered	T2,T3,T28
0	-	-	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	14237266	14200446	0	0
DmactiveOKnown_A	14237266	14200446	0	0
FpvSecCmRegWeOnehotCheck_A	14237266	70	0	0
FpvSecCmRomTlLcGateFsm_A	14237266	0	0	0
FpvSecCmSbaTlLcGateFsm_A	14237266	0	0	0
JtagRspOTdoKnown_A	734926	734922	0	0
JtagRspOTdoOeKnown_A	734926	734922	0	0
NdmresetOKnown_A	14237266	14200446	0	0
RvDmLcEnDebugVal_A	14237266	14200446	0	0
TlMemAReadyKnown_A	14237266	14200446	0	0
TlMemDValidKnown_A	14237266	14200446	0	0
TlRegsAReadyKnown_A	14237266	14200446	0	0
TlRegsDValidKnown_A	14237266	14200446	0	0
TlSbaAValidKnown_A	14237266	14200446	0	0
TlSbaDReadyKnown_A	14237266	14200446	0	0
paramCheckNrHarts	174	174	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	70	0	0
T1	8464	10	0	0
T2	73229	0	0	0
T3	236424	0	0	0
T4	178928	0	0	0
T17	4180	0	0	0
T28	101818	0	0	0
T32	8198	0	0	0
T33	4727	0	0	0
T34	16459	0	0	0
T35	17481	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T94	0	20	0	0
T95	0	10	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734926	734922	0	0
T1	1395	1395	0	0
T2	9889	9889	0	0
T3	6541	6541	0	0
T4	8607	8607	0	0
T17	1032	1032	0	0
T28	9828	9828	0	0
T32	156	156	0	0
T33	142	142	0	0
T34	783	783	0	0
T35	160	160	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734926	734922	0	0
T1	1395	1395	0	0
T2	9889	9889	0	0
T3	6541	6541	0	0
T4	8607	8607	0	0
T17	1032	1032	0	0
T28	9828	9828	0	0
T32	156	156	0	0
T33	142	142	0	0
T34	783	783	0	0
T35	160	160	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	174	174	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T28	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		33	33	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	551	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
128	1	1
131	1	1
154	1	1
236	1	1
237	1	1
239	4	4
278	1	1
288	1	1
289	1	1
320	1	1
321	1	1
322	1	1
325	1	1
326	1	1
327	1	1
328	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
334	1	1
			MISSING_ELSE
345	1	1
432	1	1
438	1	1
440	1	1
446	1	1
447	1	1
523	1	1
551	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	42	36	85.71
Logical	42	36	85.71
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Excluded		VC_COV_UNR
0	0	1	0	Excluded		VC_COV_UNR
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T52,T53

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T35
1	0	Covered	T2,T3,T32
1	1	Covered	T32,T35,T51

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T28
1	1	Covered	T2,T3,T28

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T28
1	1	Covered	T2,T3,T28

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T2,T3,T28
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T28

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T3,T32,T4
1	0	Covered	T2,T3,T28
1	1	Covered	T2,T3,T28

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T28

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
0	1	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	1	Covered	T2,T5,T58
1	1	0	1	1	Not Covered
1	1	1	0	1	Covered	T2,T3,T28
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T2,T3,T28

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T11,T13
1	1	Covered	T2,T3,T4

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	91	83	91.21
Total Bits	1082	1052	97.23
Total Bits 0->1	541	526	97.23
Total Bits 1->0	541	526	97.23

Ports	91	83	91.21
Port Bits	1082	1052	97.23
Port Bits 0->1	541	526	97.23
Port Bits 1->0	541	526	97.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T34	INPUT
lc_dft_en_i[3:0]	No	No		No		INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T5,T45,T14	Yes	T5,T45,T14	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T2,T3,T24	Yes	T2,T3,T4	INPUT
scanmode_i[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
scan_rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T2,T3,T28	Yes	T2,T3,T28	OUTPUT
dmactive_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T2,T4,T28	Yes	T2,T3,T4	OUTPUT
unavailable_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T32,T4,T82	Yes	T32,T4,T82	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T32,T82,T11	Yes	T32,T82,T83	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T32,T4,T82	Yes	T32,T4,T82	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T32,T4,T82	Yes	T32,T4,T82	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T32,T4,T28	Yes	T32,T4,T28	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T32,T4,T33	Yes	T32,T4,T35	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T32,T82,T83	Yes	T32,T82,T20	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T4,T43,T23	Yes	T4,T43,T23	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T43,T23	Yes	T4,T43,T23	OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,T4	Yes	T2,T3,T32	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T32	OUTPUT
regs_tl_d_o.d_sink	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_source[7:0]	Yes	Yes	T4,T28,T33	Yes	T4,T28,T33	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T32,T4,T33	Yes	T32,T4,T33	OUTPUT
regs_tl_d_o.d_param[2:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T43,*T23	Yes	T4,T43,T23	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T28	Yes	T2,T3,T4	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T29	Yes	T2,T4,T17	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T2,T17,T29	Yes	T2,T17,T29	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T2,T17,T29	Yes	T2,T29,T58	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T2,T4,T28	Yes	T2,T4,T28	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T28,T29	Yes	T4,T28,T29	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	T2,*T3,T4	Yes	T2,T3,T4	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_sink	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T4,T28,T29	Yes	T2,T4,T28	OUTPUT
mem_tl_d_o.d_param[2:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T71	Yes	T59,T60,T71	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_data[31:0]	Yes	Yes	T13,T60,T71	Yes	T13,T60,T71	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_address[31:2]	Yes	Yes	T88,T78,T89	Yes	T90,T88,T91	OUTPUT
sba_tl_h_o.a_source[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_size[0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T60,*T92,*T89	Yes	T60,T92,T89	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T13,T59,T71	Yes	T13,T59,T71	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T2,T5,T14	Yes	T3,T35,T93	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T32	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T34,T5	Yes	T2,T3,T5	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T3,T14,T65	Yes	T2,T3,T32	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T2,T3,T5	Yes	T2,T3,T32	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T14	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T5	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T14	INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T5	Yes	T3,T35,T5	INPUT
sba_tl_h_i.d_opcode[2:1]	No	No		No		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T13,T59,T71	Yes	T13,T59,T71	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T32,T35	Yes	T1,T32,T35	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T32,T35	Yes	T1,T32,T35	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	320	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	325	if ((ndmreset_req && (!ndmreset_pending_q)))
-3-:	327	if ((ndmreset_ack && ndmreset_pending_q))
-4-:	331	if ((ndmreset_pending_q && lc_rst_asserted))
-5-:	333	if ((ndmreset_ack && lc_rst_pending_q))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T28
0	0	1	-	-	Covered	T2,T3,T28
0	0	0	-	-	Covered	T1,T2,T3
0	-	-	1	-	Covered	T2,T3,T28
0	-	-	0	1	Covered	T2,T3,T28
0	-	-	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	14237266	14200446	0	0
DmactiveOKnown_A	14237266	14200446	0	0
FpvSecCmRegWeOnehotCheck_A	14237266	70	0	0
FpvSecCmRomTlLcGateFsm_A	14237266	0	0	0
FpvSecCmSbaTlLcGateFsm_A	14237266	0	0	0
JtagRspOTdoKnown_A	734926	734922	0	0
JtagRspOTdoOeKnown_A	734926	734922	0	0
NdmresetOKnown_A	14237266	14200446	0	0
RvDmLcEnDebugVal_A	14237266	14200446	0	0
TlMemAReadyKnown_A	14237266	14200446	0	0
TlMemDValidKnown_A	14237266	14200446	0	0
TlRegsAReadyKnown_A	14237266	14200446	0	0
TlRegsDValidKnown_A	14237266	14200446	0	0
TlSbaAValidKnown_A	14237266	14200446	0	0
TlSbaDReadyKnown_A	14237266	14200446	0	0
paramCheckNrHarts	174	174	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	70	0	0
T1	8464	10	0	0
T2	73229	0	0	0
T3	236424	0	0	0
T4	178928	0	0	0
T17	4180	0	0	0
T28	101818	0	0	0
T32	8198	0	0	0
T33	4727	0	0	0
T34	16459	0	0	0
T35	17481	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T94	0	20	0	0
T95	0	10	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734926	734922	0	0
T1	1395	1395	0	0
T2	9889	9889	0	0
T3	6541	6541	0	0
T4	8607	8607	0	0
T17	1032	1032	0	0
T28	9828	9828	0	0
T32	156	156	0	0
T33	142	142	0	0
T34	783	783	0	0
T35	160	160	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734926	734922	0	0
T1	1395	1395	0	0
T2	9889	9889	0	0
T3	6541	6541	0	0
T4	8607	8607	0	0
T17	1032	1032	0	0
T28	9828	9828	0	0
T32	156	156	0	0
T33	142	142	0	0
T34	783	783	0	0
T35	160	160	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14237266	14200446	0	0
T1	8464	7653	0	0
T2	73229	72979	0	0
T3	236424	236164	0	0
T4	178928	177977	0	0
T17	4180	4113	0	0
T28	101818	101554	0	0
T32	8198	8140	0	0
T33	4727	4657	0	0
T34	16459	16403	0	0
T35	17481	17419	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	174	174	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T17	1	1	0	0
T28	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0