Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
14236563 |
14199743 |
0 |
0 |
T1 |
8464 |
7653 |
0 |
0 |
T2 |
73229 |
72979 |
0 |
0 |
T3 |
236424 |
236164 |
0 |
0 |
T4 |
178928 |
177977 |
0 |
0 |
T17 |
4180 |
4113 |
0 |
0 |
T28 |
101818 |
101554 |
0 |
0 |
T32 |
8198 |
8140 |
0 |
0 |
T33 |
4727 |
4657 |
0 |
0 |
T34 |
16459 |
16403 |
0 |
0 |
T35 |
17481 |
17419 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
14105389 |
14068569 |
0 |
0 |
T1 |
8464 |
7653 |
0 |
0 |
T2 |
73229 |
72979 |
0 |
0 |
T3 |
236424 |
236164 |
0 |
0 |
T4 |
178928 |
177977 |
0 |
0 |
T17 |
4180 |
4113 |
0 |
0 |
T28 |
101818 |
101554 |
0 |
0 |
T32 |
8198 |
8140 |
0 |
0 |
T33 |
4727 |
4657 |
0 |
0 |
T34 |
16459 |
16403 |
0 |
0 |
T35 |
17481 |
17419 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
14237266 |
14200446 |
0 |
0 |
T1 |
8464 |
7653 |
0 |
0 |
T2 |
73229 |
72979 |
0 |
0 |
T3 |
236424 |
236164 |
0 |
0 |
T4 |
178928 |
177977 |
0 |
0 |
T17 |
4180 |
4113 |
0 |
0 |
T28 |
101818 |
101554 |
0 |
0 |
T32 |
8198 |
8140 |
0 |
0 |
T33 |
4727 |
4657 |
0 |
0 |
T34 |
16459 |
16403 |
0 |
0 |
T35 |
17481 |
17419 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
14105389 |
14068569 |
0 |
0 |
T1 |
8464 |
7653 |
0 |
0 |
T2 |
73229 |
72979 |
0 |
0 |
T3 |
236424 |
236164 |
0 |
0 |
T4 |
178928 |
177977 |
0 |
0 |
T17 |
4180 |
4113 |
0 |
0 |
T28 |
101818 |
101554 |
0 |
0 |
T32 |
8198 |
8140 |
0 |
0 |
T33 |
4727 |
4657 |
0 |
0 |
T34 |
16459 |
16403 |
0 |
0 |
T35 |
17481 |
17419 |
0 |
0 |