SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.09 | 100.00 | 85.71 | 97.23 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.09 | 100.00 | 85.71 | 97.23 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.09 | 100.00 | 85.71 | 97.23 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.09 | 100.00 | 85.71 | 97.23 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
70.34 | 86.27 | 76.47 | 57.14 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.00 | 100.00 | 100.00 | 100.00 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 85291719 | 85070799 | 0 | 0 |
gen_flops.OutputDelay_A | 42711798 | 42597171 | 0 | 1566 |
gen_no_flops.OutputDelay_A | 42579921 | 42469461 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T17 | 6 | 6 | 0 | 0 |
T28 | 6 | 6 | 0 | 0 |
T32 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
T34 | 6 | 6 | 0 | 0 |
T35 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 85291719 | 85070799 | 0 | 0 |
T1 | 50784 | 45918 | 0 | 0 |
T2 | 439374 | 437874 | 0 | 0 |
T3 | 1418544 | 1416984 | 0 | 0 |
T4 | 1073568 | 1067862 | 0 | 0 |
T17 | 25080 | 24678 | 0 | 0 |
T28 | 610908 | 609324 | 0 | 0 |
T32 | 49188 | 48840 | 0 | 0 |
T33 | 28362 | 27942 | 0 | 0 |
T34 | 98754 | 98418 | 0 | 0 |
T35 | 104886 | 104514 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42711798 | 42597171 | 0 | 1566 |
T1 | 25392 | 22860 | 0 | 9 |
T2 | 219687 | 218901 | 0 | 9 |
T3 | 709272 | 708456 | 0 | 9 |
T4 | 536784 | 533877 | 0 | 9 |
T17 | 12540 | 12330 | 0 | 9 |
T28 | 305454 | 304626 | 0 | 9 |
T32 | 24594 | 24411 | 0 | 9 |
T33 | 14181 | 13962 | 0 | 9 |
T34 | 49377 | 49200 | 0 | 9 |
T35 | 52443 | 52248 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42579921 | 42469461 | 0 | 0 |
T1 | 25392 | 22959 | 0 | 0 |
T2 | 219687 | 218937 | 0 | 0 |
T3 | 709272 | 708492 | 0 | 0 |
T4 | 536784 | 533931 | 0 | 0 |
T17 | 12540 | 12339 | 0 | 0 |
T28 | 305454 | 304662 | 0 | 0 |
T32 | 24594 | 24420 | 0 | 0 |
T33 | 14181 | 13971 | 0 | 0 |
T34 | 49377 | 49209 | 0 | 0 |
T35 | 52443 | 52257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 174 | 174 | 0 | 0 |
OutputsKnown_A | 14237266 | 14200446 | 0 | 0 |
gen_flops.OutputDelay_A | 14237266 | 14199057 | 0 | 522 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174 | 174 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14200446 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14199057 | 0 | 522 |
T1 | 8464 | 7620 | 0 | 3 |
T2 | 73229 | 72967 | 0 | 3 |
T3 | 236424 | 236152 | 0 | 3 |
T4 | 178928 | 177959 | 0 | 3 |
T17 | 4180 | 4110 | 0 | 3 |
T28 | 101818 | 101542 | 0 | 3 |
T32 | 8198 | 8137 | 0 | 3 |
T33 | 4727 | 4654 | 0 | 3 |
T34 | 16459 | 16400 | 0 | 3 |
T35 | 17481 | 17416 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 174 | 174 | 0 | 0 |
OutputsKnown_A | 14237266 | 14200446 | 0 | 0 |
gen_flops.OutputDelay_A | 14237266 | 14199057 | 0 | 522 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174 | 174 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14200446 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14199057 | 0 | 522 |
T1 | 8464 | 7620 | 0 | 3 |
T2 | 73229 | 72967 | 0 | 3 |
T3 | 236424 | 236152 | 0 | 3 |
T4 | 178928 | 177959 | 0 | 3 |
T17 | 4180 | 4110 | 0 | 3 |
T28 | 101818 | 101542 | 0 | 3 |
T32 | 8198 | 8137 | 0 | 3 |
T33 | 4727 | 4654 | 0 | 3 |
T34 | 16459 | 16400 | 0 | 3 |
T35 | 17481 | 17416 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 174 | 174 | 0 | 0 |
OutputsKnown_A | 14105389 | 14068569 | 0 | 0 |
gen_no_flops.OutputDelay_A | 14105389 | 14068569 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174 | 174 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14105389 | 14068569 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14105389 | 14068569 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 174 | 174 | 0 | 0 |
OutputsKnown_A | 14237266 | 14200446 | 0 | 0 |
gen_flops.OutputDelay_A | 14237266 | 14199057 | 0 | 522 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174 | 174 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14200446 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14199057 | 0 | 522 |
T1 | 8464 | 7620 | 0 | 3 |
T2 | 73229 | 72967 | 0 | 3 |
T3 | 236424 | 236152 | 0 | 3 |
T4 | 178928 | 177959 | 0 | 3 |
T17 | 4180 | 4110 | 0 | 3 |
T28 | 101818 | 101542 | 0 | 3 |
T32 | 8198 | 8137 | 0 | 3 |
T33 | 4727 | 4654 | 0 | 3 |
T34 | 16459 | 16400 | 0 | 3 |
T35 | 17481 | 17416 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 174 | 174 | 0 | 0 |
OutputsKnown_A | 14237266 | 14200446 | 0 | 0 |
gen_no_flops.OutputDelay_A | 14237266 | 14200446 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174 | 174 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14200446 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14200446 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 174 | 174 | 0 | 0 |
OutputsKnown_A | 14237266 | 14200446 | 0 | 0 |
gen_no_flops.OutputDelay_A | 14237266 | 14200446 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174 | 174 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14200446 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 14237266 | 14200446 | 0 | 0 |
T1 | 8464 | 7653 | 0 | 0 |
T2 | 73229 | 72979 | 0 | 0 |
T3 | 236424 | 236164 | 0 | 0 |
T4 | 178928 | 177977 | 0 | 0 |
T17 | 4180 | 4113 | 0 | 0 |
T28 | 101818 | 101554 | 0 | 0 |
T32 | 8198 | 8140 | 0 | 0 |
T33 | 4727 | 4657 | 0 | 0 |
T34 | 16459 | 16403 | 0 | 0 |
T35 | 17481 | 17419 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |