Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
103746198 |
146200 |
0 |
0 |
T11 |
0 |
6864 |
0 |
0 |
T16 |
107768 |
0 |
0 |
0 |
T24 |
0 |
4350 |
0 |
0 |
T30 |
218395 |
0 |
0 |
0 |
T35 |
33895 |
0 |
0 |
0 |
T48 |
0 |
6442 |
0 |
0 |
T53 |
198926 |
3681 |
0 |
0 |
T54 |
114383 |
0 |
0 |
0 |
T62 |
0 |
4859 |
0 |
0 |
T63 |
0 |
7124 |
0 |
0 |
T64 |
0 |
6018 |
0 |
0 |
T65 |
0 |
3025 |
0 |
0 |
T74 |
39250 |
0 |
0 |
0 |
T75 |
28757 |
0 |
0 |
0 |
T82 |
0 |
3370 |
0 |
0 |
T99 |
210635 |
0 |
0 |
0 |
T109 |
0 |
1954 |
0 |
0 |
T123 |
27591 |
0 |
0 |
0 |
T124 |
5683 |
0 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
103746198 |
13061 |
0 |
0 |
T16 |
107768 |
0 |
0 |
0 |
T24 |
0 |
1392 |
0 |
0 |
T30 |
218395 |
0 |
0 |
0 |
T35 |
33895 |
0 |
0 |
0 |
T48 |
0 |
2314 |
0 |
0 |
T53 |
198926 |
1364 |
0 |
0 |
T54 |
114383 |
0 |
0 |
0 |
T63 |
0 |
1360 |
0 |
0 |
T74 |
39250 |
0 |
0 |
0 |
T75 |
28757 |
0 |
0 |
0 |
T99 |
210635 |
0 |
0 |
0 |
T103 |
0 |
25 |
0 |
0 |
T109 |
0 |
380 |
0 |
0 |
T123 |
27591 |
0 |
0 |
0 |
T124 |
5683 |
0 |
0 |
0 |
T127 |
0 |
10 |
0 |
0 |
T160 |
0 |
30 |
0 |
0 |
T161 |
0 |
229 |
0 |
0 |
T162 |
0 |
131 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
103746198 |
10524 |
0 |
0 |
T16 |
107768 |
0 |
0 |
0 |
T24 |
0 |
1214 |
0 |
0 |
T30 |
218395 |
0 |
0 |
0 |
T35 |
33895 |
0 |
0 |
0 |
T48 |
0 |
2102 |
0 |
0 |
T53 |
198926 |
1098 |
0 |
0 |
T54 |
114383 |
0 |
0 |
0 |
T63 |
0 |
1246 |
0 |
0 |
T74 |
39250 |
0 |
0 |
0 |
T75 |
28757 |
0 |
0 |
0 |
T99 |
210635 |
0 |
0 |
0 |
T103 |
0 |
10 |
0 |
0 |
T109 |
0 |
347 |
0 |
0 |
T123 |
27591 |
0 |
0 |
0 |
T124 |
5683 |
0 |
0 |
0 |
T127 |
0 |
9 |
0 |
0 |
T160 |
0 |
31 |
0 |
0 |
T161 |
0 |
227 |
0 |
0 |
T162 |
0 |
73 |
0 |
0 |