Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.70	100.00	80.85	92.63		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.66	100.00	85.71	97.60		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	100.00	85.71	97.60		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.08	96.32	87.27	92.10	93.59	90.44	98.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	90.33	98.36	87.25		96.00	95.05	75.00
enable_checker	100.00	100.00					100.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	97.55	99.00	98.86	93.33		96.55	100.00
rv_dm_regs_csr_assert	100.00						100.00
tl_adapter_host_sba	95.14	100.00	100.00	75.71		100.00	100.00
tlul_assert_device_mem	100.00	100.00				100.00	100.00
tlul_assert_device_regs	100.00	100.00				100.00	100.00
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	88.85	90.14	73.26		100.00	80.84	100.00
u_lc_en_sync_copies	100.00	100.00					100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_flop_2sync_lc_rst_assert	100.00	100.00				100.00
u_prim_flop_2sync_lc_rst_sync	100.00	100.00				100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_mubi32_sync_late_debug_enable	100.00	100.00					100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug	100.00	100.00				100.00	100.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg_regs	98.32	98.69	99.35	93.55		100.00	100.00
u_tlul_lc_gate_rom	96.73	100.00	96.15		100.00	100.00	87.50
u_tlul_lc_gate_sba	81.96	94.49	84.00		57.14	86.67	87.50

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		33	33	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	551	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
128	1	1
131	1	1
154	1	1
236	1	1
237	1	1
239	4	4
278	1	1
288	1	1
289	1	1
320	1	1
321	1	1
322	1	1
325	1	1
326	1	1
327	1	1
328	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
334	1	1
			MISSING_ELSE
345	1	1
432	1	1
438	1	1
440	1	1
446	1	1
447	1	1
523	1	1
551	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	47	38	80.85
Logical	47	38	80.85
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T7
0	0	0	1	Covered	T66,T67,T69
0	0	1	0	Covered	T36
0	1	0	0	Not Covered
1	0	0	0	Covered	T35,T37,T70

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T33,T34
1	0	Covered	T1,T7,T3
1	1	Covered	T1,T33,T34

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T29
1	1	Covered	T3,T5,T29

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T7,T3,T13
1	1	Covered	T7,T3,T13

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T3,T13
1	0	Not Covered
1	1	Covered	T3,T5,T29

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T3,T13
1	1	Covered	T3,T5,T29

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T3,T5,T29

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Not Covered
1	0	1	1	1	Covered	T8,T58,T15
1	1	0	1	1	Not Covered
1	1	1	0	1	Covered	T3,T5,T29
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T3,T5,T29

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T41,T46
1	1	Covered	T3,T4,T5

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T3,T12,T5
1	1	Covered	T1,T2,T7

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T3,T4,T13
1	0	Covered	T3,T4,T5

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T3,T12,T5
1	1	Covered	T1,T2,T7

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	98	80	81.63
Total Bits	1140	1056	92.63
Total Bits 0->1	570	528	92.63
Total Bits 1->0	570	528	92.63

Ports	98	80	81.63
Port Bits	1140	1056	92.63
Port Bits 0->1	570	528	92.63
Port Bits 1->0	570	528	92.63

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
clk_lc_i	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
rst_ni	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
rst_lc_ni	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T7,T3,T29	Yes	T3,T29,T58	INPUT
lc_dft_en_i[3:0]	No	No		No		INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T3,T58,T71	Yes	T3,T58,T71	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T5,T6,T38	Yes	T3,T5,T6	INPUT
scanmode_i[3:0]	Yes	Yes	T3,T5,T29	Yes	T3,T5,T29	INPUT
scan_rst_ni	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
ndmreset_req_o	Yes	Yes	T3,T5,T29	Yes	T3,T5,T29	OUTPUT
dmactive_o	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	OUTPUT
debug_req_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
unavailable_i	Yes	Yes	T2,T3,T5	Yes	T3,T5,T29	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T1,T7,T3	Yes	T1,T2,T7	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T12,T40	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T5	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T38	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T53,T48,T11	Yes	T53,T48,T11	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T53,T48,T11	Yes	T53,T48,T11	OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,*T12	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T1,T3,T12	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T1,T33,T34	Yes	T1,T33,T34	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T53,*T48,*T11	Yes	T53,T48,T11	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T1,T7,T3	Yes	T1,T2,T7	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T13	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T13,T41,T46	Yes	T14,T41,T46	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T46,T47,T10	Yes	T46,T47,T10	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T5,T14,T41	Yes	T13,T5,T41	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T41,T46,T47	Yes	T14,T41,T46	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T7,T3,T4	Yes	T7,T3,T4	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T12,T13	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	T3,*T4,*T13	Yes	T7,T3,T4	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T12	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T13,T5,T6	Yes	T4,T13,T5	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T7	Yes	T3,T4,T12	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T7,T3,T4	Yes	T7,T3,T4	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T3,*T12,*T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T12,*T14,*T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T1,T7,T3	Yes	T1,T2,T7	INPUT
sba_tl_h_i.d_error	Yes	Yes	T3,T12,T5	Yes	T3,T4,T5	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T3,T12,T5	Yes	T3,T12,T5	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T12	Yes	T3,T12,T5	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T3,T12,T5	Yes	T3,T12,T5	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T3,T12,T5	Yes	T3,T4,T12	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T3,T5,T14	Yes	T3,T5,T14	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T3,T12,T5	Yes	T3,T4,T12	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T3,T5,T14	Yes	T3,T4,T5	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T3,T12,T5	Yes	T3,T4,T12	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T33,T34	Yes	T1,T33,T34	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T33,T34	Yes	T1,T33,T34	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
jtag_i.trst_n	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	320	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	325	if ((ndmreset_req && (!ndmreset_pending_q)))
-3-:	327	if ((ndmreset_ack && ndmreset_pending_q))
-4-:	331	if ((ndmreset_pending_q && lc_rst_asserted))
-5-:	333	if ((ndmreset_ack && lc_rst_pending_q))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T7
0	1	-	-	-	Covered	T7,T3,T13
0	0	1	-	-	Covered	T3,T5,T29
0	0	0	-	-	Covered	T1,T2,T7
0	-	-	1	-	Covered	T3,T5,T29
0	-	-	0	1	Covered	T3,T5,T29
0	-	-	0	0	Covered	T1,T2,T7

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	36130693	36064417	0	0
DmactiveOKnown_A	36130693	36064417	0	0
FpvSecCmRegWeOnehotCheck_A	36130693	60	0	0
FpvSecCmRomTlLcGateFsm_A	36130693	3	0	0
FpvSecCmSbaTlLcGateFsm_A	36130693	1	0	0
JtagRspOTdoKnown_A	2105355	2105312	0	0
JtagRspOTdoOeKnown_A	2105355	2105312	0	0
NdmresetOKnown_A	36130693	36064417	0	0
RvDmLcEnDebugVal_A	36130693	36064417	0	0
TlMemAReadyKnown_A	36130693	36064417	0	0
TlMemDValidKnown_A	36130693	36064417	0	0
TlRegsAReadyKnown_A	36130693	36064417	0	0
TlRegsDValidKnown_A	36130693	36064417	0	0
TlSbaAValidKnown_A	36130693	36064417	0	0
TlSbaDReadyKnown_A	36130693	36064417	0	0
paramCheckNrHarts	262	262	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	60	0	0
T30	218395	0	0	0
T31	74692	0	0	0
T35	33895	10	0	0
T37	0	10	0	0
T42	48494	0	0	0
T54	114383	0	0	0
T70	0	20	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	39250	0	0	0
T75	28757	0	0	0
T76	786451	0	0	0
T77	2721	0	0	0
T78	1723	0	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	3	0	0
T65	76056	0	0	0
T66	6425	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T79	109939	0	0	0
T80	1646	0	0	0
T81	59114	0	0	0
T82	127101	0	0	0
T83	2757	0	0	0
T84	11101	0	0	0
T85	137950	0	0	0
T86	5338	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	1	0	0
T36	3197	1	0	0
T37	15651	0	0	0
T56	7888	0	0	0
T71	113511	0	0	0
T87	3338	0	0	0
T88	1413	0	0	0
T89	549480	0	0	0
T90	112329	0	0	0
T91	23476	0	0	0
T92	32611	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2105355	2105312	0	0
T1	117	117	0	0
T2	347	347	0	0
T3	8994	8994	0	0
T4	1355	1355	0	0
T5	9515	9515	0	0
T7	119	119	0	0
T12	5847	5847	0	0
T13	635	635	0	0
T14	15056	15056	0	0
T28	14793	14793	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2105355	2105312	0	0
T1	117	117	0	0
T2	347	347	0	0
T3	8994	8994	0	0
T4	1355	1355	0	0
T5	9515	9515	0	0
T7	119	119	0	0
T12	5847	5847	0	0
T13	635	635	0	0
T14	15056	15056	0	0
T28	14793	14793	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	262	262	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T28	1	1	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		33	33	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	551	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
128	1	1
131	1	1
154	1	1
236	1	1
237	1	1
239	4	4
278	1	1
288	1	1
289	1	1
320	1	1
321	1	1
322	1	1
325	1	1
326	1	1
327	1	1
328	1	1
			MISSING_ELSE
331	1	1
332	1	1
333	1	1
334	1	1
			MISSING_ELSE
345	1	1
432	1	1
438	1	1
440	1	1
446	1	1
447	1	1
523	1	1
551	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	42	36	85.71
Logical	42	36	85.71
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	0	0	0	Covered	T1,T2,T7
0	0	0	1	Excluded	T66,T67,T69	VC_COV_UNR
0	0	1	0	Excluded	T36	VC_COV_UNR
0	1	0	0	Not Covered
1	0	0	0	Covered	T35,T37,T70

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T33,T34
1	0	Covered	T1,T7,T3
1	1	Covered	T1,T33,T34

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T29
1	1	Covered	T3,T5,T29

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T7,T3,T13
1	1	Covered	T7,T3,T13

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T7,T3,T13
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T5,T29

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T3,T13
1	1	Covered	T3,T5,T29

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T5,T29

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
0	1	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	1	Covered	T8,T58,T15
1	1	0	1	1	Not Covered
1	1	1	0	1	Covered	T3,T5,T29
1	1	1	1	0	Not Covered
1	1	1	1	1	Covered	T3,T5,T29

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T41,T46
1	1	Covered	T3,T4,T5

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T3,T12,T5
1	1	Covered	T1,T2,T7

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T3,T4,T13
1	0	Covered	T3,T4,T5

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T3,T12,T5
1	1	Covered	T1,T2,T7

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	91	84	92.31
Total Bits	1082	1056	97.60
Total Bits 0->1	541	528	97.60
Total Bits 1->0	541	528	97.60

Ports	91	84	92.31
Port Bits	1082	1056	97.60
Port Bits 0->1	541	528	97.60
Port Bits 1->0	541	528	97.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
clk_lc_i	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
rst_ni	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
rst_lc_ni	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T7,T3,T29	Yes	T3,T29,T58	INPUT
lc_dft_en_i[3:0]	No	No		No		INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T3,T58,T71	Yes	T3,T58,T71	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T5,T6,T38	Yes	T3,T5,T6	INPUT
scanmode_i[3:0]	Yes	Yes	T3,T5,T29	Yes	T3,T5,T29	INPUT
scan_rst_ni	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
ndmreset_req_o	Yes	Yes	T3,T5,T29	Yes	T3,T5,T29	OUTPUT
dmactive_o	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	OUTPUT
debug_req_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
unavailable_i	Yes	Yes	T2,T3,T5	Yes	T3,T5,T29	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T1,T7,T3	Yes	T1,T2,T7	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T12,T40	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T5	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T14	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T1,T12,T14	Yes	T1,T12,T38	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T53,T48,T11	Yes	T53,T48,T11	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T53,T48,T11	Yes	T53,T48,T11	OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,*T12	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_data[31:0]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_sink	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_source[7:0]	Yes	Yes	T1,T3,T12	Yes	T1,T2,T7	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T1,T33,T34	Yes	T1,T33,T34	OUTPUT
regs_tl_d_o.d_param[2:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T53,*T48,*T11	Yes	T53,T48,T11	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T1,T7,T3	Yes	T1,T2,T7	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T13	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T13,T41,T46	Yes	T14,T41,T46	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T46,T47,T10	Yes	T46,T47,T10	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T5,T14,T41	Yes	T13,T5,T41	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T41,T46,T47	Yes	T14,T41,T46	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T7,T3,T4	Yes	T7,T3,T4	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T12,T13	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	T3,*T4,*T13	Yes	T7,T3,T4	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T12	OUTPUT
mem_tl_d_o.d_sink	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_source[7:0]	Yes	Yes	T13,T5,T6	Yes	T4,T13,T5	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
mem_tl_d_o.d_param[2:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T7	Yes	T3,T4,T12	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T7,T3,T4	Yes	T7,T3,T4	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T3,*T12,*T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_data[31:0]	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_address[31:2]	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_source[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_size[0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_size[1]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T12,*T14,*T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T3,T12,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T1,T7,T3	Yes	T1,T2,T7	INPUT
sba_tl_h_i.d_error	Yes	Yes	T3,T12,T5	Yes	T3,T4,T5	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T3,T12,T5	Yes	T3,T12,T5	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T12	Yes	T3,T12,T5	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T3,T12,T5	Yes	T3,T12,T5	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T3,T12,T5	Yes	T3,T4,T12	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T3,T5,T14	Yes	T3,T5,T14	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T3,T12,T5	Yes	T3,T4,T12	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T3,T5,T14	Yes	T3,T4,T5	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T3,T12,T5	Yes	T3,T4,T12	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T12,T14,T28	Yes	T12,T14,T28	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T33,T34	Yes	T1,T33,T34	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T33,T34	Yes	T1,T33,T34	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
jtag_i.trst_n	Yes	Yes	T3,T12,T5	Yes	T1,T2,T7	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
IF	320	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	325	if ((ndmreset_req && (!ndmreset_pending_q)))
-3-:	327	if ((ndmreset_ack && ndmreset_pending_q))
-4-:	331	if ((ndmreset_pending_q && lc_rst_asserted))
-5-:	333	if ((ndmreset_ack && lc_rst_pending_q))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T7
0	1	-	-	-	Covered	T7,T3,T13
0	0	1	-	-	Covered	T3,T5,T29
0	0	0	-	-	Covered	T1,T2,T7
0	-	-	1	-	Covered	T3,T5,T29
0	-	-	0	1	Covered	T3,T5,T29
0	-	-	0	0	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	36130693	36064417	0	0
DmactiveOKnown_A	36130693	36064417	0	0
FpvSecCmRegWeOnehotCheck_A	36130693	60	0	0
FpvSecCmRomTlLcGateFsm_A	36130693	3	0	0
FpvSecCmSbaTlLcGateFsm_A	36130693	1	0	0
JtagRspOTdoKnown_A	2105355	2105312	0	0
JtagRspOTdoOeKnown_A	2105355	2105312	0	0
NdmresetOKnown_A	36130693	36064417	0	0
RvDmLcEnDebugVal_A	36130693	36064417	0	0
TlMemAReadyKnown_A	36130693	36064417	0	0
TlMemDValidKnown_A	36130693	36064417	0	0
TlRegsAReadyKnown_A	36130693	36064417	0	0
TlRegsDValidKnown_A	36130693	36064417	0	0
TlSbaAValidKnown_A	36130693	36064417	0	0
TlSbaDReadyKnown_A	36130693	36064417	0	0
paramCheckNrHarts	262	262	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	60	0	0
T30	218395	0	0	0
T31	74692	0	0	0
T35	33895	10	0	0
T37	0	10	0	0
T42	48494	0	0	0
T54	114383	0	0	0
T70	0	20	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	39250	0	0	0
T75	28757	0	0	0
T76	786451	0	0	0
T77	2721	0	0	0
T78	1723	0	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	3	0	0
T65	76056	0	0	0
T66	6425	1	0	0
T67	0	1	0	0
T69	0	1	0	0
T79	109939	0	0	0
T80	1646	0	0	0
T81	59114	0	0	0
T82	127101	0	0	0
T83	2757	0	0	0
T84	11101	0	0	0
T85	137950	0	0	0
T86	5338	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	1	0	0
T36	3197	1	0	0
T37	15651	0	0	0
T56	7888	0	0	0
T71	113511	0	0	0
T87	3338	0	0	0
T88	1413	0	0	0
T89	549480	0	0	0
T90	112329	0	0	0
T91	23476	0	0	0
T92	32611	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2105355	2105312	0	0
T1	117	117	0	0
T2	347	347	0	0
T3	8994	8994	0	0
T4	1355	1355	0	0
T5	9515	9515	0	0
T7	119	119	0	0
T12	5847	5847	0	0
T13	635	635	0	0
T14	15056	15056	0	0
T28	14793	14793	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2105355	2105312	0	0
T1	117	117	0	0
T2	347	347	0	0
T3	8994	8994	0	0
T4	1355	1355	0	0
T5	9515	9515	0	0
T7	119	119	0	0
T12	5847	5847	0	0
T13	635	635	0	0
T14	15056	15056	0	0
T28	14793	14793	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36130693	36064417	0	0
T1	3250	3180	0	0
T2	13267	13190	0	0
T3	634673	634169	0	0
T4	11854	11780	0	0
T5	247790	247374	0	0
T7	1727	1674	0	0
T12	88096	87848	0	0
T13	2945	2877	0	0
T14	371177	371092	0	0
T28	226372	226241	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	262	262	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T28	1	1	0	0