Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
36129792 |
36063516 |
0 |
0 |
T1 |
3250 |
3180 |
0 |
0 |
T2 |
13267 |
13190 |
0 |
0 |
T3 |
634673 |
634169 |
0 |
0 |
T4 |
11854 |
11780 |
0 |
0 |
T5 |
247790 |
247374 |
0 |
0 |
T7 |
1727 |
1674 |
0 |
0 |
T12 |
88096 |
87848 |
0 |
0 |
T13 |
2845 |
2777 |
0 |
0 |
T14 |
371177 |
371092 |
0 |
0 |
T28 |
226372 |
226241 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
36030343 |
35964067 |
0 |
0 |
T1 |
3250 |
3180 |
0 |
0 |
T2 |
13267 |
13190 |
0 |
0 |
T3 |
634673 |
634169 |
0 |
0 |
T4 |
11854 |
11780 |
0 |
0 |
T5 |
247790 |
247374 |
0 |
0 |
T7 |
1727 |
1674 |
0 |
0 |
T12 |
88096 |
87848 |
0 |
0 |
T13 |
1224 |
1156 |
0 |
0 |
T14 |
371177 |
371092 |
0 |
0 |
T28 |
226372 |
226241 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
36130693 |
36064417 |
0 |
0 |
T1 |
3250 |
3180 |
0 |
0 |
T2 |
13267 |
13190 |
0 |
0 |
T3 |
634673 |
634169 |
0 |
0 |
T4 |
11854 |
11780 |
0 |
0 |
T5 |
247790 |
247374 |
0 |
0 |
T7 |
1727 |
1674 |
0 |
0 |
T12 |
88096 |
87848 |
0 |
0 |
T13 |
2945 |
2877 |
0 |
0 |
T14 |
371177 |
371092 |
0 |
0 |
T28 |
226372 |
226241 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
36030343 |
35964067 |
0 |
0 |
T1 |
3250 |
3180 |
0 |
0 |
T2 |
13267 |
13190 |
0 |
0 |
T3 |
634673 |
634169 |
0 |
0 |
T4 |
11854 |
11780 |
0 |
0 |
T5 |
247790 |
247374 |
0 |
0 |
T7 |
1727 |
1674 |
0 |
0 |
T12 |
88096 |
87848 |
0 |
0 |
T13 |
1224 |
1156 |
0 |
0 |
T14 |
371177 |
371092 |
0 |
0 |
T28 |
226372 |
226241 |
0 |
0 |