SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
70.34 | 86.27 | 76.47 | 57.14 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.00 | 100.00 | 100.00 | 100.00 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1572 | 1572 | 0 | 0 |
OutputsKnown_A | 216683808 | 216286152 | 0 | 0 |
gen_flops.OutputDelay_A | 108392079 | 108186744 | 0 | 2358 |
gen_no_flops.OutputDelay_A | 108291729 | 108092901 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1572 | 1572 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T14 | 6 | 6 | 0 | 0 |
T28 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 216683808 | 216286152 | 0 | 0 |
T1 | 19500 | 19080 | 0 | 0 |
T2 | 79602 | 79140 | 0 | 0 |
T3 | 3808038 | 3805014 | 0 | 0 |
T4 | 71124 | 70680 | 0 | 0 |
T5 | 1486740 | 1484244 | 0 | 0 |
T7 | 10362 | 10044 | 0 | 0 |
T12 | 528576 | 527088 | 0 | 0 |
T13 | 15949 | 15541 | 0 | 0 |
T14 | 2227062 | 2226552 | 0 | 0 |
T28 | 1358232 | 1357446 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108392079 | 108186744 | 0 | 2358 |
T1 | 9750 | 9531 | 0 | 9 |
T2 | 39801 | 39561 | 0 | 9 |
T3 | 1904019 | 1902435 | 0 | 9 |
T4 | 35562 | 35331 | 0 | 9 |
T5 | 743370 | 742068 | 0 | 9 |
T7 | 5181 | 5013 | 0 | 9 |
T12 | 264288 | 263508 | 0 | 9 |
T13 | 8835 | 8622 | 0 | 9 |
T14 | 1113531 | 1113267 | 0 | 9 |
T28 | 679116 | 678705 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108291729 | 108092901 | 0 | 0 |
T1 | 9750 | 9540 | 0 | 0 |
T2 | 39801 | 39570 | 0 | 0 |
T3 | 1904019 | 1902507 | 0 | 0 |
T4 | 35562 | 35340 | 0 | 0 |
T5 | 743370 | 742122 | 0 | 0 |
T7 | 5181 | 5022 | 0 | 0 |
T12 | 264288 | 263544 | 0 | 0 |
T13 | 7114 | 6910 | 0 | 0 |
T14 | 1113531 | 1113276 | 0 | 0 |
T28 | 679116 | 678723 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 36130693 | 36064417 | 0 | 0 |
gen_flops.OutputDelay_A | 36130693 | 36062248 | 0 | 786 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36062248 | 0 | 786 |
T1 | 3250 | 3177 | 0 | 3 |
T2 | 13267 | 13187 | 0 | 3 |
T3 | 634673 | 634145 | 0 | 3 |
T4 | 11854 | 11777 | 0 | 3 |
T5 | 247790 | 247356 | 0 | 3 |
T7 | 1727 | 1671 | 0 | 3 |
T12 | 88096 | 87836 | 0 | 3 |
T13 | 2945 | 2874 | 0 | 3 |
T14 | 371177 | 371089 | 0 | 3 |
T28 | 226372 | 226235 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 36130693 | 36064417 | 0 | 0 |
gen_flops.OutputDelay_A | 36130693 | 36062248 | 0 | 786 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36062248 | 0 | 786 |
T1 | 3250 | 3177 | 0 | 3 |
T2 | 13267 | 13187 | 0 | 3 |
T3 | 634673 | 634145 | 0 | 3 |
T4 | 11854 | 11777 | 0 | 3 |
T5 | 247790 | 247356 | 0 | 3 |
T7 | 1727 | 1671 | 0 | 3 |
T12 | 88096 | 87836 | 0 | 3 |
T13 | 2945 | 2874 | 0 | 3 |
T14 | 371177 | 371089 | 0 | 3 |
T28 | 226372 | 226235 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 36030343 | 35964067 | 0 | 0 |
gen_no_flops.OutputDelay_A | 36030343 | 35964067 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36030343 | 35964067 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 1224 | 1156 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36030343 | 35964067 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 1224 | 1156 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 36130693 | 36064417 | 0 | 0 |
gen_flops.OutputDelay_A | 36130693 | 36062248 | 0 | 786 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36062248 | 0 | 786 |
T1 | 3250 | 3177 | 0 | 3 |
T2 | 13267 | 13187 | 0 | 3 |
T3 | 634673 | 634145 | 0 | 3 |
T4 | 11854 | 11777 | 0 | 3 |
T5 | 247790 | 247356 | 0 | 3 |
T7 | 1727 | 1671 | 0 | 3 |
T12 | 88096 | 87836 | 0 | 3 |
T13 | 2945 | 2874 | 0 | 3 |
T14 | 371177 | 371089 | 0 | 3 |
T28 | 226372 | 226235 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 36130693 | 36064417 | 0 | 0 |
gen_no_flops.OutputDelay_A | 36130693 | 36064417 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 36130693 | 36064417 | 0 | 0 |
gen_no_flops.OutputDelay_A | 36130693 | 36064417 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |