SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.66 | 100.00 | 85.71 | 97.60 | 100.00 | 100.00 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 36130693 | 36064417 | 0 | 0 |
gen_no_flops.OutputDelay_A | 36130693 | 36064417 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 36130693 | 36064417 | 0 | 0 |
T1 | 3250 | 3180 | 0 | 0 |
T2 | 13267 | 13190 | 0 | 0 |
T3 | 634673 | 634169 | 0 | 0 |
T4 | 11854 | 11780 | 0 | 0 |
T5 | 247790 | 247374 | 0 | 0 |
T7 | 1727 | 1674 | 0 | 0 |
T12 | 88096 | 87848 | 0 | 0 |
T13 | 2945 | 2877 | 0 | 0 |
T14 | 371177 | 371092 | 0 | 0 |
T28 | 226372 | 226241 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |