Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	286309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

640197

1

T12

2

T13

1

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	505230	1			T15	1		T17	1		T44	3
values[0x0]	177920	1			T12	2		T15	1		T16	1
values[0x1]	243356	1			T12	1		T13	2		T14	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	189336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

737170

1

T12

2

T13

1

T6

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3657	1			T9	9		T10	32		T73	17
valid_sources[0x01]	3526	1			T9	14		T10	38		T73	30
valid_sources[0x02]	4118	1			T9	12		T10	32		T73	36
valid_sources[0x03]	3424	1			T196	1		T9	12		T10	18
valid_sources[0x04]	3507	1			T9	23		T10	40		T73	25
valid_sources[0x05]	4026	1			T9	21		T10	34		T73	32
valid_sources[0x06]	3162	1			T9	20		T10	29		T73	22
valid_sources[0x07]	2954	1			T9	8		T10	13		T73	28
valid_sources[0x08]	4075	1			T66	1		T9	10		T10	37
valid_sources[0x09]	3828	1			T70	1		T9	16		T10	43
valid_sources[0x0a]	3547	1			T65	80		T9	19		T10	20
valid_sources[0x0b]	4231	1			T17	2		T9	11		T10	33
valid_sources[0x0c]	4231	1			T9	23		T10	35		T73	37
valid_sources[0x0d]	3424	1			T138	2		T9	16		T10	50
valid_sources[0x0e]	3579	1			T30	1		T67	1		T9	19
valid_sources[0x0f]	3633	1			T44	1		T92	1		T9	15
valid_sources[0x10]	3532	1			T64	1		T9	19		T10	80
valid_sources[0x11]	3625	1			T9	15		T10	64		T73	27
valid_sources[0x12]	3793	1			T37	6		T9	13		T10	28
valid_sources[0x13]	3261	1			T44	1		T64	1		T9	17
valid_sources[0x14]	4272	1			T64	2		T9	24		T10	46
valid_sources[0x15]	3592	1			T70	1		T9	14		T10	10
valid_sources[0x16]	3302	1			T9	8		T10	18		T73	29
valid_sources[0x17]	3239	1			T64	3		T70	1		T9	14
valid_sources[0x18]	4765	1			T196	2		T9	22		T10	21
valid_sources[0x19]	4048	1			T13	2		T9	14		T10	32
valid_sources[0x1a]	3375	1			T9	15		T10	35		T73	50
valid_sources[0x1b]	3614	1			T64	2		T9	23		T10	21
valid_sources[0x1c]	3151	1			T9	12		T10	37		T73	21
valid_sources[0x1d]	3958	1			T67	1		T75	1		T9	21
valid_sources[0x1e]	3488	1			T9	23		T10	22		T73	27
valid_sources[0x1f]	3377	1			T9	11		T10	33		T73	23
valid_sources[0x20]	3292	1			T145	1		T9	16		T10	36
valid_sources[0x21]	3325	1			T9	15		T10	62		T73	27
valid_sources[0x22]	3845	1			T64	1		T9	15		T10	33
valid_sources[0x23]	3635	1			T54	1		T145	1		T9	12
valid_sources[0x24]	3834	1			T9	15		T10	43		T73	36
valid_sources[0x25]	3251	1			T64	2		T53	1		T9	15
valid_sources[0x26]	3364	1			T66	1		T9	21		T10	29
valid_sources[0x27]	3600	1			T34	12		T9	16		T10	36
valid_sources[0x28]	3363	1			T70	1		T9	19		T10	36
valid_sources[0x29]	3582	1			T66	1		T9	12		T10	23
valid_sources[0x2a]	3626	1			T64	1		T9	12		T10	33
valid_sources[0x2b]	3651	1			T9	19		T10	31		T73	26
valid_sources[0x2c]	3434	1			T9	26		T10	54		T73	28
valid_sources[0x2d]	3772	1			T9	10		T10	22		T73	29
valid_sources[0x2e]	3291	1			T72	7		T70	1		T9	26
valid_sources[0x2f]	3752	1			T9	11		T10	28		T73	25
valid_sources[0x30]	3801	1			T9	15		T10	54		T73	28
valid_sources[0x31]	3749	1			T64	2		T9	14		T10	26
valid_sources[0x32]	3203	1			T64	1		T9	15		T10	29
valid_sources[0x33]	3606	1			T67	1		T9	24		T10	53
valid_sources[0x34]	3600	1			T9	12		T10	22		T73	28
valid_sources[0x35]	3434	1			T28	1		T54	1		T9	19
valid_sources[0x36]	4007	1			T64	1		T9	16		T10	21
valid_sources[0x37]	3200	1			T70	1		T9	13		T10	36
valid_sources[0x38]	3546	1			T9	12		T10	44		T73	27
valid_sources[0x39]	3492	1			T60	1		T9	11		T10	40
valid_sources[0x3a]	3520	1			T9	18		T10	49		T73	26
valid_sources[0x3b]	3607	1			T64	1		T59	9		T9	19
valid_sources[0x3c]	3399	1			T64	1		T9	6		T10	28
valid_sources[0x3d]	3544	1			T9	15		T10	33		T73	33
valid_sources[0x3e]	3687	1			T9	18		T10	26		T73	33
valid_sources[0x3f]	4290	1			T64	1		T9	21		T10	46
valid_sources[0x40]	3413	1			T64	1		T70	1		T9	16
valid_sources[0x41]	3715	1			T64	2		T9	14		T10	44
valid_sources[0x42]	3629	1			T64	1		T9	24		T10	32
valid_sources[0x43]	3199	1			T9	22		T10	29		T73	34
valid_sources[0x44]	4166	1			T64	1		T40	1		T9	16
valid_sources[0x45]	3354	1			T9	12		T10	21		T73	47
valid_sources[0x46]	3152	1			T70	1		T9	16		T10	31
valid_sources[0x47]	3694	1			T9	15		T10	22		T73	30
valid_sources[0x48]	4031	1			T64	2		T9	13		T10	42
valid_sources[0x49]	3825	1			T44	1		T9	13		T10	56
valid_sources[0x4a]	3784	1			T9	17		T10	71		T73	25
valid_sources[0x4b]	3309	1			T70	1		T9	14		T10	32
valid_sources[0x4c]	3958	1			T9	16		T10	32		T73	16
valid_sources[0x4d]	3430	1			T30	1		T145	1		T9	28
valid_sources[0x4e]	3879	1			T9	16		T10	19		T73	39
valid_sources[0x4f]	3644	1			T64	1		T9	17		T10	9
valid_sources[0x50]	3170	1			T64	1		T9	8		T10	35
valid_sources[0x51]	3607	1			T9	10		T10	23		T73	29
valid_sources[0x52]	3551	1			T9	12		T10	42		T73	26
valid_sources[0x53]	3564	1			T9	21		T10	20		T73	24
valid_sources[0x54]	3420	1			T223	2		T9	11		T10	39
valid_sources[0x55]	3428	1			T9	19		T10	19		T73	35
valid_sources[0x56]	3388	1			T9	16		T10	30		T73	34
valid_sources[0x57]	3971	1			T9	15		T10	43		T73	32
valid_sources[0x58]	3169	1			T9	13		T10	56		T73	40
valid_sources[0x59]	3592	1			T9	21		T10	34		T73	25
valid_sources[0x5a]	3246	1			T9	15		T10	27		T73	21
valid_sources[0x5b]	4318	1			T64	1		T9	20		T10	29
valid_sources[0x5c]	3862	1			T9	11		T10	38		T73	22
valid_sources[0x5d]	3472	1			T9	18		T10	26		T73	32
valid_sources[0x5e]	3515	1			T9	17		T10	68		T73	44
valid_sources[0x5f]	3629	1			T9	20		T10	32		T73	26
valid_sources[0x60]	3365	1			T64	1		T224	2		T9	17
valid_sources[0x61]	5069	1			T9	16		T10	49		T73	26
valid_sources[0x62]	3447	1			T15	1		T9	21		T10	27
valid_sources[0x63]	3607	1			T64	2		T43	1		T9	13
valid_sources[0x64]	3432	1			T9	16		T10	25		T73	27
valid_sources[0x65]	4244	1			T9	19		T10	65		T73	47
valid_sources[0x66]	3174	1			T9	21		T10	18		T73	46
valid_sources[0x67]	4475	1			T9	10		T10	66		T73	27
valid_sources[0x68]	3738	1			T64	1		T9	17		T10	39
valid_sources[0x69]	3361	1			T67	1		T9	9		T10	38
valid_sources[0x6a]	3710	1			T15	1		T84	2		T9	17
valid_sources[0x6b]	3542	1			T9	16		T10	40		T73	18
valid_sources[0x6c]	3368	1			T9	17		T10	26		T73	37
valid_sources[0x6d]	3516	1			T6	2		T64	2		T9	14
valid_sources[0x6e]	3991	1			T40	1		T70	1		T9	19
valid_sources[0x6f]	3453	1			T9	16		T10	47		T73	37
valid_sources[0x70]	3281	1			T9	28		T10	38		T73	49
valid_sources[0x71]	3416	1			T9	15		T10	18		T73	18
valid_sources[0x72]	3869	1			T9	22		T10	49		T73	32
valid_sources[0x73]	3473	1			T196	1		T9	22		T10	20
valid_sources[0x74]	3720	1			T9	11		T10	44		T73	43
valid_sources[0x75]	3338	1			T64	1		T9	15		T10	54
valid_sources[0x76]	3711	1			T70	1		T9	11		T10	43
valid_sources[0x77]	3365	1			T67	1		T9	10		T10	36
valid_sources[0x78]	3922	1			T9	21		T10	50		T73	36
valid_sources[0x79]	3491	1			T64	3		T9	8		T10	47
valid_sources[0x7a]	3753	1			T30	2		T67	1		T9	19
valid_sources[0x7b]	3303	1			T9	15		T10	70		T73	36
valid_sources[0x7c]	3495	1			T9	21		T10	52		T73	27
valid_sources[0x7d]	3336	1			T64	1		T9	22		T10	44
valid_sources[0x7e]	3354	1			T9	14		T10	43		T73	23
valid_sources[0x7f]	3442	1			T64	1		T9	21		T10	29
valid_sources[0x80]	3250	1			T64	1		T9	20		T10	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

301825

1

T44

1

T64

80

T61

5

values[0x0]

all_enables

biggest_size

169371

1

T12

1

T6

2

T17

1

values[0x1]

all_enables

biggest_size

169001

1

T12

1

T13

1

T40

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

127540

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38221	1			T9	847		T10	1478		T73	1198
values[0x0]	48016	1			T1	1		T2	1		T3	1
values[0x1]	50779	1			T12	1		T22	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

130816

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	458	1			T9	9		T73	30		T106	20
valid_sources[0x01]	513	1			T146	1		T9	15		T10	2
valid_sources[0x02]	386	1			T92	1		T70	2		T9	2
valid_sources[0x03]	654	1			T51	1		T196	1		T91	1
valid_sources[0x04]	455	1			T76	1		T9	9		T10	1
valid_sources[0x05]	559	1			T147	2		T9	16		T10	1
valid_sources[0x06]	625	1			T9	13		T117	1		T73	11
valid_sources[0x07]	460	1			T60	1		T9	8		T10	46
valid_sources[0x08]	392	1			T9	10		T73	26		T106	23
valid_sources[0x09]	795	1			T9	8		T10	1		T73	17
valid_sources[0x0a]	467	1			T9	17		T10	1		T225	1
valid_sources[0x0b]	522	1			T9	10		T10	1		T73	19
valid_sources[0x0c]	635	1			T12	1		T226	1		T9	8
valid_sources[0x0d]	385	1			T42	1		T9	15		T73	25
valid_sources[0x0e]	406	1			T9	13		T10	1		T73	23
valid_sources[0x0f]	408	1			T113	4		T147	1		T9	8
valid_sources[0x10]	590	1			T175	1		T9	5		T117	1
valid_sources[0x11]	563	1			T9	14		T10	1		T73	27
valid_sources[0x12]	643	1			T78	1		T58	1		T9	8
valid_sources[0x13]	372	1			T9	10		T10	1		T73	17
valid_sources[0x14]	410	1			T9	11		T73	21		T106	19
valid_sources[0x15]	536	1			T9	9		T10	103		T73	19
valid_sources[0x16]	363	1			T223	1		T9	14		T73	17
valid_sources[0x17]	410	1			T174	5		T9	13		T10	1
valid_sources[0x18]	668	1			T9	14		T73	23		T227	1
valid_sources[0x19]	498	1			T209	1		T9	17		T73	16
valid_sources[0x1a]	485	1			T9	9		T10	115		T73	21
valid_sources[0x1b]	417	1			T17	1		T9	18		T73	22
valid_sources[0x1c]	432	1			T9	13		T119	1		T121	6
valid_sources[0x1d]	417	1			T9	10		T10	2		T191	1
valid_sources[0x1e]	432	1			T228	1		T9	13		T10	3
valid_sources[0x1f]	618	1			T30	1		T9	18		T73	12
valid_sources[0x20]	391	1			T15	1		T9	7		T10	2
valid_sources[0x21]	534	1			T9	19		T10	84		T73	25
valid_sources[0x22]	479	1			T9	7		T73	20		T106	18
valid_sources[0x23]	614	1			T9	7		T10	153		T73	34
valid_sources[0x24]	648	1			T9	13		T10	1		T73	14
valid_sources[0x25]	417	1			T3	1		T91	1		T9	16
valid_sources[0x26]	469	1			T9	16		T73	21		T106	14
valid_sources[0x27]	406	1			T9	15		T73	25		T106	14
valid_sources[0x28]	516	1			T145	1		T9	10		T229	1
valid_sources[0x29]	443	1			T91	1		T9	8		T10	57
valid_sources[0x2a]	559	1			T9	8		T73	12		T35	6
valid_sources[0x2b]	664	1			T9	5		T10	39		T73	27
valid_sources[0x2c]	466	1			T136	1		T230	3		T9	14
valid_sources[0x2d]	358	1			T9	11		T73	16		T106	17
valid_sources[0x2e]	528	1			T9	20		T10	146		T73	18
valid_sources[0x2f]	333	1			T9	18		T73	13		T106	9
valid_sources[0x30]	441	1			T174	2		T9	8		T73	14
valid_sources[0x31]	527	1			T9	14		T10	1		T73	14
valid_sources[0x32]	587	1			T203	1		T9	16		T73	19
valid_sources[0x33]	740	1			T81	1		T70	1		T9	8
valid_sources[0x34]	545	1			T175	1		T9	13		T10	176
valid_sources[0x35]	495	1			T198	1		T9	18		T10	2
valid_sources[0x36]	346	1			T9	17		T73	30		T19	2
valid_sources[0x37]	891	1			T9	6		T10	93		T73	15
valid_sources[0x38]	883	1			T9	10		T73	25		T106	15
valid_sources[0x39]	402	1			T97	1		T9	10		T73	14
valid_sources[0x3a]	543	1			T9	17		T73	27		T106	14
valid_sources[0x3b]	573	1			T9	8		T10	6		T73	22
valid_sources[0x3c]	593	1			T46	1		T50	1		T9	12
valid_sources[0x3d]	849	1			T9	15		T10	117		T73	10
valid_sources[0x3e]	436	1			T9	18		T10	1		T73	37
valid_sources[0x3f]	457	1			T9	8		T73	17		T106	19
valid_sources[0x40]	371	1			T46	1		T176	1		T9	13
valid_sources[0x41]	471	1			T70	1		T9	12		T73	20
valid_sources[0x42]	399	1			T99	1		T9	20		T10	1
valid_sources[0x43]	568	1			T50	2		T148	1		T9	15
valid_sources[0x44]	439	1			T62	1		T9	12		T10	2
valid_sources[0x45]	422	1			T9	7		T10	33		T73	22
valid_sources[0x46]	336	1			T91	1		T9	9		T73	14
valid_sources[0x47]	636	1			T25	3		T9	14		T10	24
valid_sources[0x48]	407	1			T231	7		T9	9		T10	33
valid_sources[0x49]	536	1			T147	1		T9	14		T10	137
valid_sources[0x4a]	648	1			T77	1		T9	15		T10	1
valid_sources[0x4b]	397	1			T9	20		T10	1		T73	14
valid_sources[0x4c]	720	1			T47	1		T9	12		T10	3
valid_sources[0x4d]	483	1			T9	15		T73	16		T106	16
valid_sources[0x4e]	512	1			T13	1		T14	1		T46	1
valid_sources[0x4f]	657	1			T98	1		T57	1		T9	17
valid_sources[0x50]	442	1			T9	15		T73	14		T106	21
valid_sources[0x51]	364	1			T232	2		T233	1		T9	14
valid_sources[0x52]	914	1			T58	1		T230	1		T9	11
valid_sources[0x53]	412	1			T33	1		T67	1		T147	1
valid_sources[0x54]	526	1			T72	1		T9	16		T73	24
valid_sources[0x55]	568	1			T61	1		T138	1		T9	18
valid_sources[0x56]	553	1			T40	1		T50	1		T147	5
valid_sources[0x57]	422	1			T41	1		T176	1		T9	10
valid_sources[0x58]	382	1			T144	1		T9	19		T10	1
valid_sources[0x59]	459	1			T205	1		T9	8		T73	24
valid_sources[0x5a]	1052	1			T9	12		T10	194		T73	20
valid_sources[0x5b]	513	1			T147	2		T9	16		T234	1
valid_sources[0x5c]	692	1			T9	16		T10	23		T191	1
valid_sources[0x5d]	493	1			T50	1		T9	18		T10	1
valid_sources[0x5e]	630	1			T9	16		T73	17		T106	16
valid_sources[0x5f]	509	1			T9	11		T73	18		T106	18
valid_sources[0x60]	672	1			T9	15		T10	27		T235	1
valid_sources[0x61]	625	1			T50	1		T9	12		T117	1
valid_sources[0x62]	780	1			T93	1		T9	17		T73	21
valid_sources[0x63]	744	1			T9	18		T10	10		T73	22
valid_sources[0x64]	570	1			T224	1		T58	1		T9	11
valid_sources[0x65]	417	1			T174	3		T175	5		T34	1
valid_sources[0x66]	484	1			T9	18		T236	1		T10	40
valid_sources[0x67]	492	1			T58	1		T9	8		T73	11
valid_sources[0x68]	506	1			T9	10		T73	22		T106	21
valid_sources[0x69]	554	1			T94	1		T9	9		T10	196
valid_sources[0x6a]	533	1			T176	3		T91	1		T9	10
valid_sources[0x6b]	669	1			T29	1		T9	11		T10	135
valid_sources[0x6c]	505	1			T9	20		T10	114		T73	22
valid_sources[0x6d]	447	1			T74	1		T85	1		T9	13
valid_sources[0x6e]	724	1			T46	2		T148	1		T9	7
valid_sources[0x6f]	602	1			T115	1		T92	1		T230	3
valid_sources[0x70]	380	1			T49	2		T9	8		T10	1
valid_sources[0x71]	394	1			T30	2		T90	1		T65	1
valid_sources[0x72]	402	1			T9	14		T10	42		T73	15
valid_sources[0x73]	342	1			T69	1		T9	9		T10	3
valid_sources[0x74]	695	1			T147	2		T9	12		T73	17
valid_sources[0x75]	936	1			T9	6		T10	105		T73	26
valid_sources[0x76]	803	1			T9	15		T10	17		T73	27
valid_sources[0x77]	625	1			T9	12		T10	84		T73	15
valid_sources[0x78]	423	1			T116	1		T9	17		T10	1
valid_sources[0x79]	341	1			T68	1		T9	17		T10	1
valid_sources[0x7a]	380	1			T9	13		T73	15		T197	1
valid_sources[0x7b]	424	1			T147	1		T139	1		T9	9
valid_sources[0x7c]	400	1			T9	10		T10	1		T73	19
valid_sources[0x7d]	686	1			T83	1		T82	1		T92	1
valid_sources[0x7e]	518	1			T92	1		T9	8		T73	19
valid_sources[0x7f]	584	1			T70	2		T9	16		T73	25
valid_sources[0x80]	395	1			T9	15		T122	4		T73	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33573

1

T9

804

T10

1395

T73

1132

values[0x0]

all_enables

biggest_size

46904

1

T1

1

T2

1

T3

1

values[0x1]

all_enables

biggest_size

47063

1

T12

1

T22

1

T4

1