Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

800915

1

T12

1

T13

1

T14

1

full_word

658348

1

T12

2

T13

1

T6

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1458973	1			T12	3		T13	2		T14	1
auto[TlIntgErrCmd]	103	1			T177	3		T189	5		T190	2
auto[TlIntgErrData]	106	1			T177	4		T190	2		T213	10
auto[TlIntgErrBoth]	81	1			T177	3		T189	5		T190	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

527265

1

T15

1

T17

1

T44

3

auto[1]

931998

1

T12

3

T13

2

T14

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	223180	1			T15	1		T17	1		T44	2
auto[TlIntgErrNone]	partial	auto[1]	577467	1			T12	1		T13	1		T14	1
auto[TlIntgErrNone]	full_word	auto[0]	303965	1			T44	1		T64	80		T61	5
auto[TlIntgErrNone]	full_word	auto[1]	354361	1			T12	2		T13	1		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T177	1		T189	1		T213	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T177	2		T189	4		T190	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T190	1		T215	1		T216	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T214	1		T220	1		T212	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T177	3		T213	6		T214	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T177	1		T190	2		T213	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T220	1		T218	1		T221	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T214	1		T215	2		T210	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T177	2		T190	1		T214	1
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T177	1		T189	5		T190	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T214	1		T210	1		T217	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T211	1		T217	1		T222	1