Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 105535134 157901 0 0
late_debug_enable_rd_A 105535134 11092 0 0
late_debug_enable_regwen_rd_A 105535134 9520 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 105535134 157901 0 0
T9 85135 3271 0 0
T10 0 7614 0 0
T21 0 9784 0 0
T38 0 7323 0 0
T45 0 8253 0 0
T56 0 17851 0 0
T73 0 6501 0 0
T106 0 5511 0 0
T107 0 9156 0 0
T108 0 6783 0 0
T117 151523 0 0 0
T118 944158 0 0 0
T119 557179 0 0 0
T120 1410 0 0 0
T121 410861 0 0 0
T122 289260 0 0 0
T123 526459 0 0 0
T124 494541 0 0 0
T125 787972 0 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 105535134 11092 0 0
T45 417022 0 0 0
T71 209588 0 0 0
T107 441690 3064 0 0
T127 0 6 0 0
T131 0 41 0 0
T135 0 910 0 0
T151 0 3 0 0
T169 0 37 0 0
T177 0 17 0 0
T178 0 133 0 0
T179 0 9 0 0
T180 0 200 0 0
T181 141156 0 0 0
T182 164420 0 0 0
T183 105935 0 0 0
T184 165381 0 0 0
T185 210463 0 0 0
T186 136743 0 0 0
T187 613649 0 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 105535134 9520 0 0
T45 417022 0 0 0
T71 209588 0 0 0
T107 441690 2941 0 0
T131 0 52 0 0
T132 0 4 0 0
T151 0 6 0 0
T169 0 2 0 0
T177 0 21 0 0
T178 0 67 0 0
T179 0 25 0 0
T180 0 200 0 0
T181 141156 0 0 0
T182 164420 0 0 0
T183 105935 0 0 0
T184 165381 0 0 0
T185 210463 0 0 0
T186 136743 0 0 0
T187 613649 0 0 0
T188 0 161 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%