Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T3
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
19431 |
0 |
0 |
T1 |
9172 |
74 |
0 |
0 |
T2 |
29962 |
62 |
0 |
0 |
T3 |
83578 |
42 |
0 |
0 |
T4 |
1820 |
3 |
0 |
0 |
T12 |
24545 |
11 |
0 |
0 |
T13 |
35305 |
7 |
0 |
0 |
T14 |
10721 |
5 |
0 |
0 |
T15 |
31720 |
7 |
0 |
0 |
T16 |
77600 |
8 |
0 |
0 |
T22 |
47184 |
79 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
44851213 |
0 |
0 |
T1 |
9172 |
9089 |
0 |
0 |
T2 |
29962 |
29849 |
0 |
0 |
T3 |
83578 |
83291 |
0 |
0 |
T4 |
1820 |
1723 |
0 |
0 |
T12 |
24545 |
24252 |
0 |
0 |
T13 |
35305 |
35054 |
0 |
0 |
T14 |
10721 |
10576 |
0 |
0 |
T15 |
31720 |
31322 |
0 |
0 |
T16 |
77600 |
76328 |
0 |
0 |
T22 |
47184 |
47078 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
44851213 |
0 |
0 |
T1 |
9172 |
9089 |
0 |
0 |
T2 |
29962 |
29849 |
0 |
0 |
T3 |
83578 |
83291 |
0 |
0 |
T4 |
1820 |
1723 |
0 |
0 |
T12 |
24545 |
24252 |
0 |
0 |
T13 |
35305 |
35054 |
0 |
0 |
T14 |
10721 |
10576 |
0 |
0 |
T15 |
31720 |
31322 |
0 |
0 |
T16 |
77600 |
76328 |
0 |
0 |
T22 |
47184 |
47078 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
44851213 |
0 |
0 |
T1 |
9172 |
9089 |
0 |
0 |
T2 |
29962 |
29849 |
0 |
0 |
T3 |
83578 |
83291 |
0 |
0 |
T4 |
1820 |
1723 |
0 |
0 |
T12 |
24545 |
24252 |
0 |
0 |
T13 |
35305 |
35054 |
0 |
0 |
T14 |
10721 |
10576 |
0 |
0 |
T15 |
31720 |
31322 |
0 |
0 |
T16 |
77600 |
76328 |
0 |
0 |
T22 |
47184 |
47078 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
19431 |
0 |
0 |
T1 |
9172 |
74 |
0 |
0 |
T2 |
29962 |
62 |
0 |
0 |
T3 |
83578 |
42 |
0 |
0 |
T4 |
1820 |
3 |
0 |
0 |
T12 |
24545 |
11 |
0 |
0 |
T13 |
35305 |
7 |
0 |
0 |
T14 |
10721 |
5 |
0 |
0 |
T15 |
31720 |
7 |
0 |
0 |
T16 |
77600 |
8 |
0 |
0 |
T22 |
47184 |
79 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T3
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
19431 |
0 |
0 |
T1 |
9172 |
74 |
0 |
0 |
T2 |
29962 |
62 |
0 |
0 |
T3 |
83578 |
42 |
0 |
0 |
T4 |
1820 |
3 |
0 |
0 |
T12 |
24545 |
11 |
0 |
0 |
T13 |
35305 |
7 |
0 |
0 |
T14 |
10721 |
5 |
0 |
0 |
T15 |
31720 |
7 |
0 |
0 |
T16 |
77600 |
8 |
0 |
0 |
T22 |
47184 |
79 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
44851213 |
0 |
0 |
T1 |
9172 |
9089 |
0 |
0 |
T2 |
29962 |
29849 |
0 |
0 |
T3 |
83578 |
83291 |
0 |
0 |
T4 |
1820 |
1723 |
0 |
0 |
T12 |
24545 |
24252 |
0 |
0 |
T13 |
35305 |
35054 |
0 |
0 |
T14 |
10721 |
10576 |
0 |
0 |
T15 |
31720 |
31322 |
0 |
0 |
T16 |
77600 |
76328 |
0 |
0 |
T22 |
47184 |
47078 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
44851213 |
0 |
0 |
T1 |
9172 |
9089 |
0 |
0 |
T2 |
29962 |
29849 |
0 |
0 |
T3 |
83578 |
83291 |
0 |
0 |
T4 |
1820 |
1723 |
0 |
0 |
T12 |
24545 |
24252 |
0 |
0 |
T13 |
35305 |
35054 |
0 |
0 |
T14 |
10721 |
10576 |
0 |
0 |
T15 |
31720 |
31322 |
0 |
0 |
T16 |
77600 |
76328 |
0 |
0 |
T22 |
47184 |
47078 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
44851213 |
0 |
0 |
T1 |
9172 |
9089 |
0 |
0 |
T2 |
29962 |
29849 |
0 |
0 |
T3 |
83578 |
83291 |
0 |
0 |
T4 |
1820 |
1723 |
0 |
0 |
T12 |
24545 |
24252 |
0 |
0 |
T13 |
35305 |
35054 |
0 |
0 |
T14 |
10721 |
10576 |
0 |
0 |
T15 |
31720 |
31322 |
0 |
0 |
T16 |
77600 |
76328 |
0 |
0 |
T22 |
47184 |
47078 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
45360514 |
19431 |
0 |
0 |
T1 |
9172 |
74 |
0 |
0 |
T2 |
29962 |
62 |
0 |
0 |
T3 |
83578 |
42 |
0 |
0 |
T4 |
1820 |
3 |
0 |
0 |
T12 |
24545 |
11 |
0 |
0 |
T13 |
35305 |
7 |
0 |
0 |
T14 |
10721 |
5 |
0 |
0 |
T15 |
31720 |
7 |
0 |
0 |
T16 |
77600 |
8 |
0 |
0 |
T22 |
47184 |
79 |
0 |
0 |