Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7093750 7092258 0 0
selKnown1 50228115 50226623 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7093750 7092258 0 0
T1 16404 16402 0 0
T2 13786 13784 0 0
T3 11810 11808 0 0
T4 654 652 0 0
T7 2 1 0 0
T8 4 2 0 0
T12 2804 2802 0 0
T13 1858 1856 0 0
T14 1048 1046 0 0
T15 1770 1768 0 0
T16 1718 1716 0 0
T17 1 0 0 0
T18 1 0 0 0
T22 17712 17710 0 0
T26 1 0 0 0
T27 2 0 0 0
T30 0 18 0 0
T44 1 0 0 0
T46 0 9 0 0
T47 0 2 0 0
T48 0 20 0 0
T59 2 0 0 0
T61 1 0 0 0
T64 1 0 0 0
T76 0 2 0 0
T77 0 1 0 0
T78 0 1 0 0
T86 2 0 0 0
T90 0 2 0 0
T99 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 50228115 50226623 0 0
T1 17374 17372 0 0
T2 36855 36853 0 0
T3 89483 89481 0 0
T4 2147 2145 0 0
T12 25947 25945 0 0
T13 36234 36232 0 0
T14 11245 11243 0 0
T15 32605 32603 0 0
T16 78459 78457 0 0
T22 56040 56038 0 0
T23 0 6 0 0
T30 0 12 0 0
T33 2 0 0 0
T43 2 0 0 0
T46 10 8 0 0
T47 4 2 0 0
T48 22 20 0 0
T49 2 0 0 0
T52 0 2 0 0
T53 2 0 0 0
T76 2 0 0 0
T81 2 0 0 0
T82 0 2 0 0
T85 0 2 0 0
T87 0 20 0 0
T93 0 4 0 0
T99 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2226054 2225791 0 0
selKnown1 45360514 45360251 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2226054 2225791 0 0
T1 8202 8201 0 0
T2 6893 6892 0 0
T3 5905 5904 0 0
T4 327 326 0 0
T12 1402 1401 0 0
T13 929 928 0 0
T14 524 523 0 0
T15 885 884 0 0
T16 859 858 0 0
T22 8856 8855 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 45360514 45360251 0 0
T1 9172 9171 0 0
T2 29962 29961 0 0
T3 83578 83577 0 0
T4 1820 1819 0 0
T12 24545 24544 0 0
T13 35305 35304 0 0
T14 10721 10720 0 0
T15 31720 31719 0 0
T16 77600 77599 0 0
T22 47184 47183 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 787 524 0 0
selKnown1 740 477 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 787 524 0 0
T8 2 1 0 0
T18 1 0 0 0
T23 0 3 0 0
T27 1 0 0 0
T30 0 9 0 0
T42 1 0 0 0
T43 1 0 0 0
T46 5 4 0 0
T47 0 1 0 0
T48 0 10 0 0
T52 0 1 0 0
T59 1 0 0 0
T76 2 1 0 0
T77 0 1 0 0
T86 1 0 0 0
T90 0 1 0 0
T99 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 740 477 0 0
T23 0 3 0 0
T30 0 6 0 0
T33 1 0 0 0
T43 1 0 0 0
T46 5 4 0 0
T47 2 1 0 0
T48 11 10 0 0
T49 1 0 0 0
T52 0 1 0 0
T53 1 0 0 0
T76 1 0 0 0
T81 1 0 0 0
T82 0 1 0 0
T85 0 1 0 0
T87 0 10 0 0
T93 0 2 0 0
T99 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4865203 4864720 0 0
selKnown1 4865202 4864719 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4865203 4864720 0 0
T1 8202 8201 0 0
T2 6893 6892 0 0
T3 5905 5904 0 0
T4 327 326 0 0
T12 1402 1401 0 0
T13 929 928 0 0
T14 524 523 0 0
T15 885 884 0 0
T16 859 858 0 0
T22 8856 8855 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 4865202 4864719 0 0
T1 8202 8201 0 0
T2 6893 6892 0 0
T3 5905 5904 0 0
T4 327 326 0 0
T12 1402 1401 0 0
T13 929 928 0 0
T14 524 523 0 0
T15 885 884 0 0
T16 859 858 0 0
T22 8856 8855 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1706 1223 0 0
selKnown1 1659 1176 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1706 1223 0 0
T7 2 1 0 0
T8 2 1 0 0
T17 1 0 0 0
T26 1 0 0 0
T27 1 0 0 0
T30 0 9 0 0
T44 1 0 0 0
T46 0 5 0 0
T47 0 1 0 0
T48 0 10 0 0
T59 1 0 0 0
T61 1 0 0 0
T64 1 0 0 0
T76 0 1 0 0
T78 0 1 0 0
T86 1 0 0 0
T90 0 1 0 0
T99 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1659 1176 0 0
T23 0 3 0 0
T30 0 6 0 0
T33 1 0 0 0
T43 1 0 0 0
T46 5 4 0 0
T47 2 1 0 0
T48 11 10 0 0
T49 1 0 0 0
T52 0 1 0 0
T53 1 0 0 0
T76 1 0 0 0
T81 1 0 0 0
T82 0 1 0 0
T85 0 1 0 0
T87 0 10 0 0
T93 0 2 0 0
T99 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%