Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113711473 |
126463 |
0 |
0 |
T10 |
0 |
6996 |
0 |
0 |
T11 |
0 |
11972 |
0 |
0 |
T18 |
0 |
6145 |
0 |
0 |
T37 |
0 |
5241 |
0 |
0 |
T50 |
0 |
6542 |
0 |
0 |
T51 |
0 |
6035 |
0 |
0 |
T65 |
175191 |
0 |
0 |
0 |
T68 |
152607 |
4778 |
0 |
0 |
T81 |
0 |
9802 |
0 |
0 |
T112 |
0 |
10233 |
0 |
0 |
T121 |
0 |
233 |
0 |
0 |
T122 |
438945 |
0 |
0 |
0 |
T123 |
590497 |
0 |
0 |
0 |
T124 |
3980 |
0 |
0 |
0 |
T125 |
92535 |
0 |
0 |
0 |
T126 |
73842 |
0 |
0 |
0 |
T127 |
882903 |
0 |
0 |
0 |
T128 |
483962 |
0 |
0 |
0 |
T129 |
246739 |
0 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113711473 |
14151 |
0 |
0 |
T10 |
0 |
2434 |
0 |
0 |
T37 |
0 |
1923 |
0 |
0 |
T50 |
334526 |
2113 |
0 |
0 |
T51 |
0 |
1967 |
0 |
0 |
T131 |
0 |
6 |
0 |
0 |
T132 |
0 |
14 |
0 |
0 |
T134 |
0 |
10 |
0 |
0 |
T174 |
0 |
5 |
0 |
0 |
T175 |
0 |
48 |
0 |
0 |
T176 |
0 |
82 |
0 |
0 |
T177 |
513349 |
0 |
0 |
0 |
T178 |
259080 |
0 |
0 |
0 |
T179 |
191553 |
0 |
0 |
0 |
T180 |
100753 |
0 |
0 |
0 |
T181 |
113438 |
0 |
0 |
0 |
T182 |
138299 |
0 |
0 |
0 |
T183 |
211237 |
0 |
0 |
0 |
T184 |
122636 |
0 |
0 |
0 |
T185 |
751768 |
0 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113711473 |
11971 |
0 |
0 |
T10 |
0 |
2145 |
0 |
0 |
T37 |
0 |
1704 |
0 |
0 |
T50 |
334526 |
1898 |
0 |
0 |
T51 |
0 |
1743 |
0 |
0 |
T131 |
0 |
14 |
0 |
0 |
T132 |
0 |
23 |
0 |
0 |
T134 |
0 |
11 |
0 |
0 |
T174 |
0 |
7 |
0 |
0 |
T175 |
0 |
31 |
0 |
0 |
T176 |
0 |
97 |
0 |
0 |
T177 |
513349 |
0 |
0 |
0 |
T178 |
259080 |
0 |
0 |
0 |
T179 |
191553 |
0 |
0 |
0 |
T180 |
100753 |
0 |
0 |
0 |
T181 |
113438 |
0 |
0 |
0 |
T182 |
138299 |
0 |
0 |
0 |
T183 |
211237 |
0 |
0 |
0 |
T184 |
122636 |
0 |
0 |
0 |
T185 |
751768 |
0 |
0 |
0 |