Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.55 100.00 85.11 92.63 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 97.61 100.00 90.48 97.60 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.61 100.00 90.48 97.60 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.62 96.27 89.82 92.10 94.67 90.10 98.74


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
dap 90.47 98.36 91.95 92.00 95.05 75.00
enable_checker 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
i_tlul_adapter_reg 97.55 99.00 98.86 93.33 96.55 100.00
rv_dm_regs_csr_assert 100.00 100.00
tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 100.00 100.00 100.00 100.00
tlul_assert_device_regs 100.00 100.00 100.00 100.00
tlul_assert_host_sba 94.30 100.00 85.71 97.18
u_dm_top 88.83 89.97 73.80 100.00 80.37 100.00
u_lc_en_sync_copies 100.00 100.00 100.00
u_pm_en_sync 100.00 100.00 100.00 100.00
u_prim_clock_mux2 100.00 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
u_prim_rst_n_mux2 100.00 100.00 100.00 100.00
u_reg_regs 98.32 98.69 99.35 93.55 100.00 100.00
u_tlul_lc_gate_rom 96.09 100.00 96.15 100.00 96.77 87.50
u_tlul_lc_gate_sba 90.53 94.49 84.00 100.00 86.67 87.50

Line Coverage for Module : rv_dm
Line No.TotalCoveredPercent
TOTAL3333100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
ALWAYS3201111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55111100.00

121 // implemented inside the vendored-in rv_dm module from the PULP project. 122 1/1 assign mem_tl_win_h2d = mem_tl_d_i; Tests: T1 T2 T3  123 1/1 assign mem_tl_d_o = mem_tl_win_d2h; Tests: T1 T2 T3  124 125 // Alerts 126 logic [NumAlerts-1:0] alert_test, alerts; 127 128 1/1 assign alerts[0] = regs_intg_error | rom_intg_error | Tests: T1 T2 T3  129 sba_gate_intg_error | rom_gate_intg_error; 130 131 1/1 assign alert_test = { Tests: T1 T2 T3  132 regs_reg2hw.alert_test.q & 133 regs_reg2hw.alert_test.qe 134 }; 135 136 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx 137 prim_alert_sender #( 138 .AsyncOn(AlertAsyncOn[i]), 139 .IsFatal(1'b1) 140 ) u_prim_alert_sender ( 141 .clk_i, 142 .rst_ni, 143 .alert_test_i ( alert_test[i] ), 144 .alert_req_i ( alerts[0] ), 145 .alert_ack_o ( ), 146 .alert_state_o ( ), 147 .alert_rx_i ( alert_rx_i[i] ), 148 .alert_tx_o ( alert_tx_o[i] ) 149 ); 150 end 151 152 // Decode multibit scanmode enable 153 logic testmode; 154 1/1 assign testmode = mubi4_test_true_strict(scanmode_i); Tests: T44 T30 T25  155 156 /////////////////////// 157 // Life Cycle Gating // 158 /////////////////////// 159 160 // Debug enable gating. 161 localparam int LcEnDebugReqVal = 4 - 1; 162 localparam int LcEnResetReqVal = LcEnDebugReqVal + NrHarts; 163 // +1 to get number of bits and another +1 because LcEnLastPos is one more than LcEnResetReq. 164 localparam int RvDmLcEnSize = $clog2(LcEnResetReqVal + 2); 165 typedef enum logic [RvDmLcEnSize-1:0] { 166 LcEnFetch, 167 LcEnRom, 168 LcEnSba, 169 // LcEnDebugReq[NrHarts], <= this unfortunately does not work - SV-LRM mandates the use of 170 // integral numbers. Parameters are not allowed in this context. 171 LcEnDebugReq, 172 // The above literal accommodates NrHarts number of debug requests - so we number the next 173 // literal accordingly. 174 LcEnResetReq = RvDmLcEnSize'(LcEnResetReqVal), 175 // LcEnLastPos must immediately follow LcEnResetReq to calculate RvDmLcEnSize. 176 LcEnLastPos 177 } rv_dm_lc_en_e; 178 // These must be equal so that the difference between LcEnResetReq and LcEnDebugReq is NrHarts. 179 `ASSERT(RvDmLcEnDebugVal_A, int'(LcEnDebugReq) == LcEnDebugReqVal) 180 181 // debug enable gating 182 typedef enum logic [3:0] { 183 PmEnDmiReq, 184 PmEnJtagIn, 185 PmEnJtagOut, 186 PmEnLastPos 187 } rv_dm_pm_en_e; 188 189 lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; 190 prim_lc_sync #( 191 .NumCopies(1) 192 ) u_prim_lc_sync_lc_hw_debug_en ( 193 .clk_i, 194 .rst_ni, 195 .lc_en_i(lc_hw_debug_en_i), 196 .lc_en_o({lc_hw_debug_en}) 197 ); 198 199 lc_ctrl_pkg::lc_tx_t lc_dft_en; 200 prim_lc_sync #( 201 .NumCopies(1) 202 ) u_prim_lc_sync_lc_dft_en ( 203 .clk_i, 204 .rst_ni, 205 .lc_en_i(lc_dft_en_i), 206 .lc_en_o({lc_dft_en}) 207 ); 208 209 prim_mubi_pkg::mubi8_t [lc_ctrl_pkg::TxWidth-1:0] otp_dis_rv_dm_late_debug; 210 prim_mubi8_sync #( 211 .NumCopies (lc_ctrl_pkg::TxWidth) 212 ) u_prim_mubi8_sync_otp_dis_rv_dm_late_debug ( 213 .clk_i, 214 .rst_ni, 215 .mubi_i(otp_dis_rv_dm_late_debug_i), 216 .mubi_o(otp_dis_rv_dm_late_debug) 217 ); 218 219 prim_mubi_pkg::mubi32_t [lc_ctrl_pkg::TxWidth-1:0] late_debug_enable; 220 prim_mubi32_sync #( 221 .NumCopies (lc_ctrl_pkg::TxWidth), 222 .AsyncOn(0) // No synchronization required since the input signal is already synchronous. 223 ) u_prim_mubi32_sync_late_debug_enable ( 224 .clk_i, 225 .rst_ni, 226 .mubi_i(prim_mubi_pkg::mubi32_t'(regs_reg2hw.late_debug_enable)), 227 .mubi_o(late_debug_enable) 228 ); 229 230 // SEC_CM: DM_EN.CTRL.LC_GATED 231 // This implements a hardened MuBi multiplexor circuit where each output bitlane has its own 232 // associated comparators for the enablement condition. 233 logic [lc_ctrl_pkg::TxWidth-1:0] lc_hw_debug_en_raw; 234 logic [lc_ctrl_pkg::TxWidth-1:0] lc_dft_en_raw; 235 logic [lc_ctrl_pkg::TxWidth-1:0] lc_hw_debug_en_gated_raw; 236 1/1 assign lc_hw_debug_en_raw = lc_hw_debug_en; Tests: T1 T2 T3  237 1/1 assign lc_dft_en_raw = lc_dft_en; Tests: T1 T2 T3  238 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_mubi_mux 239 4/4 assign lc_hw_debug_en_gated_raw[k] = (mubi8_test_true_strict(otp_dis_rv_dm_late_debug[k]) || Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  240 mubi32_test_true_strict(late_debug_enable[k])) ? 241 lc_hw_debug_en_raw[k] : 242 lc_dft_en_raw[k]; 243 end 244 245 // The lc_hw_debug_en_gated signal modulates gating logic on the bus-side of the RV_DM. 246 // The pinmux_hw_debug_en signal on the other hand modulates the TAP side of the RV_DM. 247 // In order for the RV_DM to remain response during a NDM reset request, the TAP side 248 // is not further modulated with the LATE_DEBUG_ENABLE CSR. 249 lc_ctrl_pkg::lc_tx_t [LcEnLastPos-1:0] lc_hw_debug_en_gated; 250 prim_lc_sync #( 251 .NumCopies(int'(LcEnLastPos)), 252 .AsyncOn(0) // No synchronization required since the input signal is already synchronous. 253 ) u_lc_en_sync_copies ( 254 .clk_i, 255 .rst_ni, 256 .lc_en_i(lc_ctrl_pkg::lc_tx_t'(lc_hw_debug_en_gated_raw)), 257 .lc_en_o(lc_hw_debug_en_gated) 258 ); 259 260 lc_ctrl_pkg::lc_tx_t [PmEnLastPos-1:0] pinmux_hw_debug_en; 261 prim_lc_sync #( 262 .NumCopies(int'(PmEnLastPos)) 263 ) u_pm_en_sync ( 264 .clk_i, 265 .rst_ni, 266 .lc_en_i(pinmux_hw_debug_en_i), 267 .lc_en_o(pinmux_hw_debug_en) 268 ); 269 270 dm::dmi_req_t dmi_req; 271 dm::dmi_resp_t dmi_rsp; 272 logic dmi_req_valid, dmi_req_ready; 273 logic dmi_rsp_valid, dmi_rsp_ready; 274 logic dmi_rst_n; 275 276 logic dmi_en; 277 // SEC_CM: DM_EN.CTRL.LC_GATED 278 1/1 assign dmi_en = lc_tx_test_true_strict(pinmux_hw_debug_en[PmEnDmiReq]); Tests: T1 T2 T3  279 280 //////////////////////// 281 // NDM Reset Tracking // 282 //////////////////////// 283 284 logic reset_req_en; 285 logic ndmreset_req, ndmreset_ack; 286 logic ndmreset_req_qual; 287 // SEC_CM: DM_EN.CTRL.LC_GATED 288 1/1 assign reset_req_en = lc_tx_test_true_strict(lc_hw_debug_en_gated[LcEnResetReq]); Tests: T1 T2 T3  289 1/1 assign ndmreset_req_o = ndmreset_req_qual & reset_req_en; Tests: T1 T2 T3  290 291 // Sample the processor reset to detect lc reset assertion. 292 logic lc_rst_asserted_async; 293 prim_flop_2sync #( 294 .Width(1), 295 .ResetValue(1) // Resets to 1 to indicate assertion. 296 ) u_prim_flop_2sync_lc_rst_assert ( 297 .clk_i, // Use RV_DM clock 298 .rst_ni(rst_lc_ni), // Use LC reset here that resets the entire system except the RV_DM. 299 .d_i(1'b0), // Set to 0 to indicate deassertion. 300 .q_o(lc_rst_asserted_async) 301 ); 302 303 // Note that the output of the above flops can be metastable at reset assertion, since the reset 304 // signal is coming from a different clock domain and has not been synchronized with clk_i. 305 logic lc_rst_asserted; 306 prim_flop_2sync #( 307 .Width(1) 308 ) u_prim_flop_2sync_lc_rst_sync ( 309 .clk_i, 310 .rst_ni, 311 .d_i(lc_rst_asserted_async), 312 .q_o(lc_rst_asserted) 313 ); 314 315 // The acknowledgement pulse sets the dmstatus.allhavereset / dmstatus.anyhavereset registers in 316 // RV_DM. It should only be asserted once an NDM reset request has been fully completed. 317 logic ndmreset_pending_q; 318 logic lc_rst_pending_q; 319 always_ff @(posedge clk_i or negedge rst_ni) begin : p_ndm_reset 320 1/1 if (!rst_ni) begin Tests: T1 T2 T3  321 1/1 ndmreset_pending_q <= 1'b0; Tests: T1 T2 T3  322 1/1 lc_rst_pending_q <= 1'b0; Tests: T1 T2 T3  323 end else begin 324 // Only set this if there was no previous pending NDM request. 325 1/1 if (ndmreset_req && !ndmreset_pending_q) begin Tests: T1 T2 T3  326 1/1 ndmreset_pending_q <= 1'b1; Tests: T1 T14 T86  327 1/1 end else if (ndmreset_ack && ndmreset_pending_q) begin Tests: T1 T2 T3  328 1/1 ndmreset_pending_q <= 1'b0; Tests: T14 T30 T25  329 end MISSING_ELSE 330 // We only track lc resets that are asserted during an active ndm reset request.. 331 1/1 if (ndmreset_pending_q && lc_rst_asserted) begin Tests: T1 T2 T3  332 1/1 lc_rst_pending_q <= 1'b1; Tests: T14 T30 T25  333 1/1 end else if (ndmreset_ack && lc_rst_pending_q) begin Tests: T1 T2 T3  334 1/1 lc_rst_pending_q <= 1'b0; Tests: T14 T30 T25  335 end MISSING_ELSE 336 end 337 end 338 339 // In order to ACK the following conditions must be met 340 // 1) an NDM reset request was asserted and is pending 341 // 2) a lc reset was asserted after the NDM reset request 342 // 3) the NDM reset request was deasserted 343 // 4) the NDM lc request was deasserted 344 // 5) the debug module has been ungated for operation (depending on LC state, OTP config and CSR) 345 1/1 assign ndmreset_ack = ndmreset_pending_q && Tests: T1 T2 T3  346 lc_rst_pending_q && 347 !ndmreset_req && 348 !lc_rst_asserted && 349 reset_req_en; 350 351 ///////////////////////////////////////// 352 // System Bus Access Port (TL-UL Host) // 353 ///////////////////////////////////////// 354 355 logic host_req; 356 logic [BusWidth-1:0] host_add; 357 logic host_we; 358 logic [BusWidth-1:0] host_wdata; 359 logic [BusWidth/8-1:0] host_be; 360 logic host_gnt; 361 logic host_r_valid; 362 logic [BusWidth-1:0] host_r_rdata; 363 logic host_r_err; 364 logic host_r_other_err; 365 366 // SEC_CM: DM_EN.CTRL.LC_GATED 367 // SEC_CM: SBA_TL_LC_GATE.FSM.SPARSE 368 tlul_pkg::tl_h2d_t sba_tl_h_o_int; 369 tlul_pkg::tl_d2h_t sba_tl_h_i_int; 370 tlul_lc_gate #( 371 .NumGatesPerDirection(2) 372 ) u_tlul_lc_gate_sba ( 373 .clk_i, 374 .rst_ni, 375 .tl_h2d_i(sba_tl_h_o_int), 376 .tl_d2h_o(sba_tl_h_i_int), 377 .tl_h2d_o(sba_tl_h_o), 378 .tl_d2h_i(sba_tl_h_i), 379 .lc_en_i (lc_hw_debug_en_gated[LcEnSba]), 380 .err_o (sba_gate_intg_error), 381 .flush_req_i('0), 382 .flush_ack_o(), 383 .resp_pending_o() 384 ); 385 386 tlul_adapter_host #( 387 .MAX_REQS(1), 388 .EnableDataIntgGen(1), 389 .EnableRspDataIntgCheck(1) 390 ) tl_adapter_host_sba ( 391 .clk_i, 392 .rst_ni, 393 .req_i (host_req), 394 .instr_type_i (prim_mubi_pkg::MuBi4False), 395 .gnt_o (host_gnt), 396 .addr_i (host_add), 397 .we_i (host_we), 398 .wdata_i (host_wdata), 399 .wdata_intg_i ('0), 400 .be_i (host_be), 401 .valid_o (host_r_valid), 402 .rdata_o (host_r_rdata), 403 .rdata_intg_o (), 404 .err_o (host_r_err), 405 // Note: This bus integrity error is not connected to the alert due to a few reasons: 406 // 1) the SBA module is not active in production life cycle states. 407 // 2) there is value in being able to accept incoming transactions with integrity 408 // errors during test / debug life cycle states so that the system can be debugged 409 // without triggering alerts. 410 // 3) the error condition is hooked up to an error CSR that can be read out by the debugger 411 // via JTAG so that bus integrity errors can be told appart from regular bus errors. 412 .intg_err_o (host_r_other_err), 413 .tl_o (sba_tl_h_o_int), 414 .tl_i (sba_tl_h_i_int) 415 ); 416 417 ////////////////////////////////////// 418 // Debug Memory Port (TL-UL Device) // 419 ////////////////////////////////////// 420 421 logic device_req; 422 logic device_we; 423 logic device_re; 424 logic [BusWidth/8-1:0] device_be; 425 logic [BusWidth-1:0] device_wdata; 426 logic [BusWidth-1:0] device_rdata; 427 logic device_err; 428 429 logic [BusWidth-1:0] device_addr_aligned; 430 logic [MemAw-1:0] device_addr; 431 432 1/1 assign device_addr_aligned = BusWidth'(device_addr); Tests: T1 T2 T3  433 434 logic [NrHarts-1:0] debug_req_en; 435 logic [NrHarts-1:0] debug_req; 436 for (genvar i = 0; i < NrHarts; i++) begin : gen_debug_req_hart 437 // SEC_CM: DM_EN.CTRL.LC_GATED 438 1/1 assign debug_req_en[i] = lc_tx_test_true_strict(lc_hw_debug_en_gated[LcEnDebugReq + i]); Tests: T1 T2 T3  439 end 440 1/1 assign debug_req_o = debug_req & debug_req_en; Tests: T1 T2 T3  441 442 // Gating of JTAG signals 443 jtag_pkg::jtag_req_t jtag_in_int; 444 jtag_pkg::jtag_rsp_t jtag_out_int; 445 446 1/1 assign jtag_in_int = (lc_tx_test_true_strict(pinmux_hw_debug_en[PmEnJtagIn])) ? jtag_i : '0; Tests: T1 T2 T3  447 1/1 assign jtag_o = (lc_tx_test_true_strict(pinmux_hw_debug_en[PmEnJtagOut])) ? jtag_out_int : '0; Tests: T1 T2 T3  448 449 // Bound-in DPI module replaces the TAP 450 `ifndef DMIDirectTAP 451 452 logic tck_muxed; 453 logic trst_n_muxed; 454 prim_clock_mux2 #( 455 .NoFpgaBufG(1'b1) 456 ) u_prim_clock_mux2 ( 457 .clk0_i(jtag_in_int.tck), 458 .clk1_i(clk_i), 459 .sel_i (testmode), 460 .clk_o (tck_muxed) 461 ); 462 463 prim_clock_mux2 #( 464 .NoFpgaBufG(1'b1) 465 ) u_prim_rst_n_mux2 ( 466 .clk0_i(jtag_in_int.trst_n), 467 .clk1_i(scan_rst_ni), 468 .sel_i (testmode), 469 .clk_o (trst_n_muxed) 470 ); 471 472 // JTAG TAP 473 dmi_jtag #( 474 .IdcodeValue (IdcodeValue), 475 .NumDmiWordAbits(7) 476 ) dap ( 477 .clk_i (clk_i), 478 .rst_ni (rst_ni), 479 .testmode_i (testmode), 480 .test_rst_ni (scan_rst_ni), 481 482 .dmi_rst_no (dmi_rst_n), 483 .dmi_req_o (dmi_req), 484 .dmi_req_valid_o (dmi_req_valid), 485 .dmi_req_ready_i (dmi_req_ready & dmi_en), 486 487 .dmi_resp_i (dmi_rsp ), 488 .dmi_resp_ready_o (dmi_rsp_ready), 489 .dmi_resp_valid_i (dmi_rsp_valid & dmi_en), 490 491 //JTAG 492 .tck_i (tck_muxed), 493 .tms_i (jtag_in_int.tms), 494 .trst_ni (trst_n_muxed), 495 .td_i (jtag_in_int.tdi), 496 .td_o (jtag_out_int.tdo), 497 .tdo_oe_o (jtag_out_int.tdo_oe) 498 ); 499 `endif 500 501 // SEC_CM: DM_EN.CTRL.LC_GATED 502 // SEC_CM: MEM_TL_LC_GATE.FSM.SPARSE 503 tlul_pkg::tl_h2d_t mem_tl_win_h2d_gated; 504 tlul_pkg::tl_d2h_t mem_tl_win_d2h_gated; 505 tlul_lc_gate #( 506 .NumGatesPerDirection(2) 507 ) u_tlul_lc_gate_rom ( 508 .clk_i, 509 .rst_ni, 510 .tl_h2d_i(mem_tl_win_h2d), 511 .tl_d2h_o(mem_tl_win_d2h), 512 .tl_h2d_o(mem_tl_win_h2d_gated), 513 .tl_d2h_i(mem_tl_win_d2h_gated), 514 .flush_req_i(ndmreset_req), 515 .flush_ack_o(ndmreset_req_qual), 516 .resp_pending_o(), 517 .lc_en_i (lc_hw_debug_en_gated[LcEnRom]), 518 .err_o (rom_gate_intg_error) 519 ); 520 521 prim_mubi_pkg::mubi4_t en_ifetch; 522 // SEC_CM: DM_EN.CTRL.LC_GATED, EXEC.CTRL.MUBI 523 1/1 assign en_ifetch = mubi4_bool_to_mubi(lc_tx_test_true_strict(lc_hw_debug_en_gated[LcEnFetch])); Tests: T1 T2 T3  524 525 tlul_adapter_reg #( 526 .CmdIntgCheck (1), 527 .EnableRspIntgGen (1), 528 .EnableDataIntgGen(1), 529 .RegAw (MemAw), 530 .RegDw (BusWidth), 531 .AccessLatency (1) 532 ) i_tlul_adapter_reg ( 533 .clk_i, 534 .rst_ni, 535 .tl_i (mem_tl_win_h2d_gated), 536 .tl_o (mem_tl_win_d2h_gated), 537 // SEC_CM: EXEC.CTRL.MUBI 538 .en_ifetch_i (en_ifetch), 539 // SEC_CM: BUS.INTEGRITY 540 .intg_error_o(rom_intg_error), 541 .re_o (device_re), 542 .we_o (device_we), 543 .addr_o (device_addr), 544 .wdata_o (device_wdata), 545 .be_o (device_be), 546 .busy_i (1'b0), 547 .rdata_i (device_rdata), 548 .error_i (device_err) 549 ); 550 551 1/1 assign device_req = device_we || device_re; Tests: T1 T2 T3 

Cond Coverage for Module : rv_dm
TotalCoveredPercent
Conditions474085.11
Logical474085.11
Non-Logical00
Event00

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT43,T57
0010CoveredT49,T53
0100Not Covered
1000CoveredT48,T87,T88

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT45,T46,T47
10CoveredT3,T6,T12
11CoveredT45,T46,T47

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T30,T25
11CoveredT1,T14,T44

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T14,T86
11CoveredT1,T14,T86

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------
-1--2-StatusTests
01CoveredT1,T14,T86
10Not Covered
11CoveredT14,T30,T25

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------
-1--2-StatusTests
01CoveredT1,T6,T12
10CoveredT1,T14,T86
11CoveredT14,T30,T25

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------
-1--2-StatusTests
01CoveredT14,T30,T25
10Not Covered
11CoveredT14,T30,T25

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----
-1--2--3--4--5-StatusTests
01111Not Covered
10111CoveredT1,T44,T56
11011CoveredT14,T30,T25
11101CoveredT14,T30,T25
11110Not Covered
11111CoveredT14,T30,T25

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86,T89,T55
11CoveredT1,T3,T12

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T90,T43
11CoveredT1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T14,T42
10CoveredT3,T6,T12

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T90,T43
11CoveredT1,T2,T3

Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 98 80 81.63
Total Bits 1140 1056 92.63
Total Bits 0->1 570 528 92.63
Total Bits 1->0 570 528 92.63

Ports 98 80 81.63
Port Bits 1140 1056 92.63
Port Bits 0->1 570 528 92.63
Port Bits 1->0 570 528 92.63

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_lc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T43,T44,T30 Yes T1,T2,T3 INPUT
rst_lc_ni Yes Yes T14,T43,T44 Yes T1,T2,T3 INPUT
next_dm_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
lc_hw_debug_en_i[3:0] Yes Yes T86,T25,T91 Yes T86,T25,T89 INPUT
lc_dft_en_i[3:0] No No No INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T7,T30,T25 Yes T7,T30,T25 INPUT
otp_dis_rv_dm_late_debug_i[7:0] Yes Yes T30,T92,T59 Yes T30,T92,T59 INPUT
scanmode_i[3:0] Yes Yes T44,T30,T25 Yes T30,T25,T92 INPUT
scan_rst_ni Yes Yes T43,T44,T30 Yes T1,T2,T3 INPUT
ndmreset_req_o Yes Yes T1,T14,T44 Yes T1,T14,T44 OUTPUT
dmactive_o Yes Yes T1,T8,T43 Yes T1,T2,T3 OUTPUT
debug_req_o Yes Yes T1,T28,T42 Yes T1,T3,T12 OUTPUT
unavailable_i Yes Yes T1,T5,T28 Yes T1,T4,T5 INPUT
regs_tl_d_i.d_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T3,T31,T7 Yes T6,T31,T7 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T31,T15,T43 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T6,T31,T42 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T3,T6,T42 Yes T3,T31,T42 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T3,T31,T7 Yes T31,T7,T42 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T3,T6,T31 Yes T3,T31,T7 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T3,T6,T7 Yes T31,T24,T29 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_error Yes Yes T68,T50,T37 Yes T68,T50,T37 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] Yes Yes T68,T50,T37 Yes T68,T50,T37 OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T43,*T44,*T45 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T43,T44,T30 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[7:0] Yes Yes T45,T30,T25 Yes T12,T28,T14 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T45,T47,T93 Yes T45,T47,T93 OUTPUT
regs_tl_d_o.d_param[2:0] No No No OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T68,*T50,*T37 Yes T68,T50,T37 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_i.d_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T1,T6,T13 Yes T6,T31,T42 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T13,T28,T42 Yes T13,T42,T8 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T6,T13,T42 Yes T1,T6,T13 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T6,T13,T42 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T1,T6,T13 Yes T6,T13,T31 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T6,T13,T42 Yes T6,T42,T8 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T1,T6,T13 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T6,T13,T14 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T6,T13,T31 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T1,T6,T13 Yes T6,T13,T8 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T1,T6,T13 Yes T6,T13,T31 INPUT
mem_tl_d_i.a_valid Yes Yes T3,T6,T12 Yes T3,T6,T12 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T14,T41,T43 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T42,T69,T71 Yes T42,T69,T71 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T31,*T14,*T42 Yes T3,T6,T12 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T3,T6,T12 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[7:0] Yes Yes T14,T69,T71 Yes T3,T6,T13 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T31,T66,T30 Yes T12,T13,T31 OUTPUT
mem_tl_d_o.d_param[2:0] No No No OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T28,T14,T42 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T3,T6,T12 Yes T3,T6,T12 OUTPUT
sba_tl_h_o.d_ready Yes Yes T14,T43,T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T2,T14,T20 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T14,*T43,*T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T14,T43,T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] No No No OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T2,T14,T20 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_source[7:0] No No No OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T14,T43,T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_param[2:0] No No No OUTPUT
sba_tl_h_o.a_opcode[0] Yes Yes *T2,*T20,*T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T2,T14,T20 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_valid Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_i.a_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T2,T20,T44 Yes T12,T29,T20 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T2,T12,T24 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T2,T24,T20 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T24,T20,T44 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_sink Yes Yes T29,T20,T44 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T24,T20,T44 Yes T29,T20,T44 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T24,T29,T20 Yes T20,T44,T94 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T12,T20,T44 Yes T20,T44,T94 INPUT
sba_tl_h_i.d_opcode[2:0] Yes Yes T2,T20,T44 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_valid Yes Yes T2,T20,T21 Yes T2,T20,T21 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T45,T48 Yes T43,T45,T48 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T45,T48 Yes T43,T45,T48 OUTPUT
jtag_i.tdi Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.trst_n Yes Yes T7,T24,T43 Yes T1,T2,T3 INPUT
jtag_i.tms Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.tck Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_o.tdo_oe Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
jtag_o.tdo Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_dm
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 320 7 7 100.00


320 if (!rst_ni) begin -1- 321 ndmreset_pending_q <= 1'b0; ==> 322 lc_rst_pending_q <= 1'b0; 323 end else begin 324 // Only set this if there was no previous pending NDM request. 325 if (ndmreset_req && !ndmreset_pending_q) begin -2- 326 ndmreset_pending_q <= 1'b1; ==> 327 end else if (ndmreset_ack && ndmreset_pending_q) begin -3- 328 ndmreset_pending_q <= 1'b0; ==> 329 end MISSING_ELSE ==> 330 // We only track lc resets that are asserted during an active ndm reset request.. 331 if (ndmreset_pending_q && lc_rst_asserted) begin -4- 332 lc_rst_pending_q <= 1'b1; ==> 333 end else if (ndmreset_ack && lc_rst_pending_q) begin -5- 334 lc_rst_pending_q <= 1'b0; ==> 335 end MISSING_ELSE ==>

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T14,T86
0 0 1 - - Covered T14,T30,T25
0 0 0 - - Covered T1,T2,T3
0 - - 1 - Covered T14,T30,T25
0 - - 0 1 Covered T14,T30,T25
0 - - 0 0 Covered T1,T2,T3


Assert Coverage for Module : rv_dm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 57068224 57005635 0 0
DmactiveOKnown_A 57068224 57005635 0 0
FpvSecCmRegWeOnehotCheck_A 57068224 80 0 0
FpvSecCmRomTlLcGateFsm_A 57068224 2 0 0
FpvSecCmSbaTlLcGateFsm_A 57068224 2 0 0
JtagRspOTdoKnown_A 2588102 2588034 0 0
JtagRspOTdoOeKnown_A 2588102 2588034 0 0
NdmresetOKnown_A 57068224 57005635 0 0
RvDmLcEnDebugVal_A 57068224 57005635 0 0
TlMemAReadyKnown_A 57068224 57005635 0 0
TlMemDValidKnown_A 57068224 57005635 0 0
TlRegsAReadyKnown_A 57068224 57005635 0 0
TlRegsDValidKnown_A 57068224 57005635 0 0
TlSbaAValidKnown_A 57068224 57005635 0 0
TlSbaDReadyKnown_A 57068224 57005635 0 0
paramCheckNrHarts 262 262 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 80 0 0
T21 200349 0 0 0
T25 34635 0 0 0
T32 39529 0 0 0
T48 27629 20 0 0
T54 61882 0 0 0
T58 12951 0 0 0
T60 13668 0 0 0
T67 3361 0 0 0
T72 2071 0 0 0
T83 7943 0 0 0
T87 0 10 0 0
T88 0 10 0 0
T95 0 20 0 0
T96 0 20 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 2 0 0
T16 6932 0 0 0
T30 19106 0 0 0
T43 5584 1 0 0
T44 207714 0 0 0
T45 4938 0 0 0
T48 27629 0 0 0
T57 0 1 0 0
T94 1448 0 0 0
T97 8078 0 0 0
T98 8099 0 0 0
T99 13727 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 2 0 0
T47 2172 0 0 0
T49 1228 1 0 0
T53 8609 1 0 0
T55 10855 0 0 0
T56 5620 0 0 0
T85 338350 0 0 0
T91 75768 0 0 0
T100 125319 0 0 0
T101 67288 0 0 0
T102 2301 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2588102 2588034 0 0
T1 3574 3574 0 0
T2 5567 5567 0 0
T3 842 842 0 0
T4 388 388 0 0
T5 1276 1276 0 0
T6 370 370 0 0
T12 578 578 0 0
T13 1329 1329 0 0
T28 769 769 0 0
T31 901 901 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2588102 2588034 0 0
T1 3574 3574 0 0
T2 5567 5567 0 0
T3 842 842 0 0
T4 388 388 0 0
T5 1276 1276 0 0
T6 370 370 0 0
T12 578 578 0 0
T13 1329 1329 0 0
T28 769 769 0 0
T31 901 901 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T28 1 1 0 0
T31 1 1 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL3333100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
ALWAYS3201111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55111100.00

121 // implemented inside the vendored-in rv_dm module from the PULP project. 122 1/1 assign mem_tl_win_h2d = mem_tl_d_i; Tests: T1 T2 T3  123 1/1 assign mem_tl_d_o = mem_tl_win_d2h; Tests: T1 T2 T3  124 125 // Alerts 126 logic [NumAlerts-1:0] alert_test, alerts; 127 128 1/1 assign alerts[0] = regs_intg_error | rom_intg_error | Tests: T1 T2 T3  129 sba_gate_intg_error | rom_gate_intg_error; 130 131 1/1 assign alert_test = { Tests: T1 T2 T3  132 regs_reg2hw.alert_test.q & 133 regs_reg2hw.alert_test.qe 134 }; 135 136 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx 137 prim_alert_sender #( 138 .AsyncOn(AlertAsyncOn[i]), 139 .IsFatal(1'b1) 140 ) u_prim_alert_sender ( 141 .clk_i, 142 .rst_ni, 143 .alert_test_i ( alert_test[i] ), 144 .alert_req_i ( alerts[0] ), 145 .alert_ack_o ( ), 146 .alert_state_o ( ), 147 .alert_rx_i ( alert_rx_i[i] ), 148 .alert_tx_o ( alert_tx_o[i] ) 149 ); 150 end 151 152 // Decode multibit scanmode enable 153 logic testmode; 154 1/1 assign testmode = mubi4_test_true_strict(scanmode_i); Tests: T44 T30 T25  155 156 /////////////////////// 157 // Life Cycle Gating // 158 /////////////////////// 159 160 // Debug enable gating. 161 localparam int LcEnDebugReqVal = 4 - 1; 162 localparam int LcEnResetReqVal = LcEnDebugReqVal + NrHarts; 163 // +1 to get number of bits and another +1 because LcEnLastPos is one more than LcEnResetReq. 164 localparam int RvDmLcEnSize = $clog2(LcEnResetReqVal + 2); 165 typedef enum logic [RvDmLcEnSize-1:0] { 166 LcEnFetch, 167 LcEnRom, 168 LcEnSba, 169 // LcEnDebugReq[NrHarts], <= this unfortunately does not work - SV-LRM mandates the use of 170 // integral numbers. Parameters are not allowed in this context. 171 LcEnDebugReq, 172 // The above literal accommodates NrHarts number of debug requests - so we number the next 173 // literal accordingly. 174 LcEnResetReq = RvDmLcEnSize'(LcEnResetReqVal), 175 // LcEnLastPos must immediately follow LcEnResetReq to calculate RvDmLcEnSize. 176 LcEnLastPos 177 } rv_dm_lc_en_e; 178 // These must be equal so that the difference between LcEnResetReq and LcEnDebugReq is NrHarts. 179 `ASSERT(RvDmLcEnDebugVal_A, int'(LcEnDebugReq) == LcEnDebugReqVal) 180 181 // debug enable gating 182 typedef enum logic [3:0] { 183 PmEnDmiReq, 184 PmEnJtagIn, 185 PmEnJtagOut, 186 PmEnLastPos 187 } rv_dm_pm_en_e; 188 189 lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; 190 prim_lc_sync #( 191 .NumCopies(1) 192 ) u_prim_lc_sync_lc_hw_debug_en ( 193 .clk_i, 194 .rst_ni, 195 .lc_en_i(lc_hw_debug_en_i), 196 .lc_en_o({lc_hw_debug_en}) 197 ); 198 199 lc_ctrl_pkg::lc_tx_t lc_dft_en; 200 prim_lc_sync #( 201 .NumCopies(1) 202 ) u_prim_lc_sync_lc_dft_en ( 203 .clk_i, 204 .rst_ni, 205 .lc_en_i(lc_dft_en_i), 206 .lc_en_o({lc_dft_en}) 207 ); 208 209 prim_mubi_pkg::mubi8_t [lc_ctrl_pkg::TxWidth-1:0] otp_dis_rv_dm_late_debug; 210 prim_mubi8_sync #( 211 .NumCopies (lc_ctrl_pkg::TxWidth) 212 ) u_prim_mubi8_sync_otp_dis_rv_dm_late_debug ( 213 .clk_i, 214 .rst_ni, 215 .mubi_i(otp_dis_rv_dm_late_debug_i), 216 .mubi_o(otp_dis_rv_dm_late_debug) 217 ); 218 219 prim_mubi_pkg::mubi32_t [lc_ctrl_pkg::TxWidth-1:0] late_debug_enable; 220 prim_mubi32_sync #( 221 .NumCopies (lc_ctrl_pkg::TxWidth), 222 .AsyncOn(0) // No synchronization required since the input signal is already synchronous. 223 ) u_prim_mubi32_sync_late_debug_enable ( 224 .clk_i, 225 .rst_ni, 226 .mubi_i(prim_mubi_pkg::mubi32_t'(regs_reg2hw.late_debug_enable)), 227 .mubi_o(late_debug_enable) 228 ); 229 230 // SEC_CM: DM_EN.CTRL.LC_GATED 231 // This implements a hardened MuBi multiplexor circuit where each output bitlane has its own 232 // associated comparators for the enablement condition. 233 logic [lc_ctrl_pkg::TxWidth-1:0] lc_hw_debug_en_raw; 234 logic [lc_ctrl_pkg::TxWidth-1:0] lc_dft_en_raw; 235 logic [lc_ctrl_pkg::TxWidth-1:0] lc_hw_debug_en_gated_raw; 236 1/1 assign lc_hw_debug_en_raw = lc_hw_debug_en; Tests: T1 T2 T3  237 1/1 assign lc_dft_en_raw = lc_dft_en; Tests: T1 T2 T3  238 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_mubi_mux 239 4/4 assign lc_hw_debug_en_gated_raw[k] = (mubi8_test_true_strict(otp_dis_rv_dm_late_debug[k]) || Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  240 mubi32_test_true_strict(late_debug_enable[k])) ? 241 lc_hw_debug_en_raw[k] : 242 lc_dft_en_raw[k]; 243 end 244 245 // The lc_hw_debug_en_gated signal modulates gating logic on the bus-side of the RV_DM. 246 // The pinmux_hw_debug_en signal on the other hand modulates the TAP side of the RV_DM. 247 // In order for the RV_DM to remain response during a NDM reset request, the TAP side 248 // is not further modulated with the LATE_DEBUG_ENABLE CSR. 249 lc_ctrl_pkg::lc_tx_t [LcEnLastPos-1:0] lc_hw_debug_en_gated; 250 prim_lc_sync #( 251 .NumCopies(int'(LcEnLastPos)), 252 .AsyncOn(0) // No synchronization required since the input signal is already synchronous. 253 ) u_lc_en_sync_copies ( 254 .clk_i, 255 .rst_ni, 256 .lc_en_i(lc_ctrl_pkg::lc_tx_t'(lc_hw_debug_en_gated_raw)), 257 .lc_en_o(lc_hw_debug_en_gated) 258 ); 259 260 lc_ctrl_pkg::lc_tx_t [PmEnLastPos-1:0] pinmux_hw_debug_en; 261 prim_lc_sync #( 262 .NumCopies(int'(PmEnLastPos)) 263 ) u_pm_en_sync ( 264 .clk_i, 265 .rst_ni, 266 .lc_en_i(pinmux_hw_debug_en_i), 267 .lc_en_o(pinmux_hw_debug_en) 268 ); 269 270 dm::dmi_req_t dmi_req; 271 dm::dmi_resp_t dmi_rsp; 272 logic dmi_req_valid, dmi_req_ready; 273 logic dmi_rsp_valid, dmi_rsp_ready; 274 logic dmi_rst_n; 275 276 logic dmi_en; 277 // SEC_CM: DM_EN.CTRL.LC_GATED 278 1/1 assign dmi_en = lc_tx_test_true_strict(pinmux_hw_debug_en[PmEnDmiReq]); Tests: T1 T2 T3  279 280 //////////////////////// 281 // NDM Reset Tracking // 282 //////////////////////// 283 284 logic reset_req_en; 285 logic ndmreset_req, ndmreset_ack; 286 logic ndmreset_req_qual; 287 // SEC_CM: DM_EN.CTRL.LC_GATED 288 1/1 assign reset_req_en = lc_tx_test_true_strict(lc_hw_debug_en_gated[LcEnResetReq]); Tests: T1 T2 T3  289 1/1 assign ndmreset_req_o = ndmreset_req_qual & reset_req_en; Tests: T1 T2 T3  290 291 // Sample the processor reset to detect lc reset assertion. 292 logic lc_rst_asserted_async; 293 prim_flop_2sync #( 294 .Width(1), 295 .ResetValue(1) // Resets to 1 to indicate assertion. 296 ) u_prim_flop_2sync_lc_rst_assert ( 297 .clk_i, // Use RV_DM clock 298 .rst_ni(rst_lc_ni), // Use LC reset here that resets the entire system except the RV_DM. 299 .d_i(1'b0), // Set to 0 to indicate deassertion. 300 .q_o(lc_rst_asserted_async) 301 ); 302 303 // Note that the output of the above flops can be metastable at reset assertion, since the reset 304 // signal is coming from a different clock domain and has not been synchronized with clk_i. 305 logic lc_rst_asserted; 306 prim_flop_2sync #( 307 .Width(1) 308 ) u_prim_flop_2sync_lc_rst_sync ( 309 .clk_i, 310 .rst_ni, 311 .d_i(lc_rst_asserted_async), 312 .q_o(lc_rst_asserted) 313 ); 314 315 // The acknowledgement pulse sets the dmstatus.allhavereset / dmstatus.anyhavereset registers in 316 // RV_DM. It should only be asserted once an NDM reset request has been fully completed. 317 logic ndmreset_pending_q; 318 logic lc_rst_pending_q; 319 always_ff @(posedge clk_i or negedge rst_ni) begin : p_ndm_reset 320 1/1 if (!rst_ni) begin Tests: T1 T2 T3  321 1/1 ndmreset_pending_q <= 1'b0; Tests: T1 T2 T3  322 1/1 lc_rst_pending_q <= 1'b0; Tests: T1 T2 T3  323 end else begin 324 // Only set this if there was no previous pending NDM request. 325 1/1 if (ndmreset_req && !ndmreset_pending_q) begin Tests: T1 T2 T3  326 1/1 ndmreset_pending_q <= 1'b1; Tests: T1 T14 T86  327 1/1 end else if (ndmreset_ack && ndmreset_pending_q) begin Tests: T1 T2 T3  328 1/1 ndmreset_pending_q <= 1'b0; Tests: T14 T30 T25  329 end MISSING_ELSE 330 // We only track lc resets that are asserted during an active ndm reset request.. 331 1/1 if (ndmreset_pending_q && lc_rst_asserted) begin Tests: T1 T2 T3  332 1/1 lc_rst_pending_q <= 1'b1; Tests: T14 T30 T25  333 1/1 end else if (ndmreset_ack && lc_rst_pending_q) begin Tests: T1 T2 T3  334 1/1 lc_rst_pending_q <= 1'b0; Tests: T14 T30 T25  335 end MISSING_ELSE 336 end 337 end 338 339 // In order to ACK the following conditions must be met 340 // 1) an NDM reset request was asserted and is pending 341 // 2) a lc reset was asserted after the NDM reset request 342 // 3) the NDM reset request was deasserted 343 // 4) the NDM lc request was deasserted 344 // 5) the debug module has been ungated for operation (depending on LC state, OTP config and CSR) 345 1/1 assign ndmreset_ack = ndmreset_pending_q && Tests: T1 T2 T3  346 lc_rst_pending_q && 347 !ndmreset_req && 348 !lc_rst_asserted && 349 reset_req_en; 350 351 ///////////////////////////////////////// 352 // System Bus Access Port (TL-UL Host) // 353 ///////////////////////////////////////// 354 355 logic host_req; 356 logic [BusWidth-1:0] host_add; 357 logic host_we; 358 logic [BusWidth-1:0] host_wdata; 359 logic [BusWidth/8-1:0] host_be; 360 logic host_gnt; 361 logic host_r_valid; 362 logic [BusWidth-1:0] host_r_rdata; 363 logic host_r_err; 364 logic host_r_other_err; 365 366 // SEC_CM: DM_EN.CTRL.LC_GATED 367 // SEC_CM: SBA_TL_LC_GATE.FSM.SPARSE 368 tlul_pkg::tl_h2d_t sba_tl_h_o_int; 369 tlul_pkg::tl_d2h_t sba_tl_h_i_int; 370 tlul_lc_gate #( 371 .NumGatesPerDirection(2) 372 ) u_tlul_lc_gate_sba ( 373 .clk_i, 374 .rst_ni, 375 .tl_h2d_i(sba_tl_h_o_int), 376 .tl_d2h_o(sba_tl_h_i_int), 377 .tl_h2d_o(sba_tl_h_o), 378 .tl_d2h_i(sba_tl_h_i), 379 .lc_en_i (lc_hw_debug_en_gated[LcEnSba]), 380 .err_o (sba_gate_intg_error), 381 .flush_req_i('0), 382 .flush_ack_o(), 383 .resp_pending_o() 384 ); 385 386 tlul_adapter_host #( 387 .MAX_REQS(1), 388 .EnableDataIntgGen(1), 389 .EnableRspDataIntgCheck(1) 390 ) tl_adapter_host_sba ( 391 .clk_i, 392 .rst_ni, 393 .req_i (host_req), 394 .instr_type_i (prim_mubi_pkg::MuBi4False), 395 .gnt_o (host_gnt), 396 .addr_i (host_add), 397 .we_i (host_we), 398 .wdata_i (host_wdata), 399 .wdata_intg_i ('0), 400 .be_i (host_be), 401 .valid_o (host_r_valid), 402 .rdata_o (host_r_rdata), 403 .rdata_intg_o (), 404 .err_o (host_r_err), 405 // Note: This bus integrity error is not connected to the alert due to a few reasons: 406 // 1) the SBA module is not active in production life cycle states. 407 // 2) there is value in being able to accept incoming transactions with integrity 408 // errors during test / debug life cycle states so that the system can be debugged 409 // without triggering alerts. 410 // 3) the error condition is hooked up to an error CSR that can be read out by the debugger 411 // via JTAG so that bus integrity errors can be told appart from regular bus errors. 412 .intg_err_o (host_r_other_err), 413 .tl_o (sba_tl_h_o_int), 414 .tl_i (sba_tl_h_i_int) 415 ); 416 417 ////////////////////////////////////// 418 // Debug Memory Port (TL-UL Device) // 419 ////////////////////////////////////// 420 421 logic device_req; 422 logic device_we; 423 logic device_re; 424 logic [BusWidth/8-1:0] device_be; 425 logic [BusWidth-1:0] device_wdata; 426 logic [BusWidth-1:0] device_rdata; 427 logic device_err; 428 429 logic [BusWidth-1:0] device_addr_aligned; 430 logic [MemAw-1:0] device_addr; 431 432 1/1 assign device_addr_aligned = BusWidth'(device_addr); Tests: T1 T2 T3  433 434 logic [NrHarts-1:0] debug_req_en; 435 logic [NrHarts-1:0] debug_req; 436 for (genvar i = 0; i < NrHarts; i++) begin : gen_debug_req_hart 437 // SEC_CM: DM_EN.CTRL.LC_GATED 438 1/1 assign debug_req_en[i] = lc_tx_test_true_strict(lc_hw_debug_en_gated[LcEnDebugReq + i]); Tests: T1 T2 T3  439 end 440 1/1 assign debug_req_o = debug_req & debug_req_en; Tests: T1 T2 T3  441 442 // Gating of JTAG signals 443 jtag_pkg::jtag_req_t jtag_in_int; 444 jtag_pkg::jtag_rsp_t jtag_out_int; 445 446 1/1 assign jtag_in_int = (lc_tx_test_true_strict(pinmux_hw_debug_en[PmEnJtagIn])) ? jtag_i : '0; Tests: T1 T2 T3  447 1/1 assign jtag_o = (lc_tx_test_true_strict(pinmux_hw_debug_en[PmEnJtagOut])) ? jtag_out_int : '0; Tests: T1 T2 T3  448 449 // Bound-in DPI module replaces the TAP 450 `ifndef DMIDirectTAP 451 452 logic tck_muxed; 453 logic trst_n_muxed; 454 prim_clock_mux2 #( 455 .NoFpgaBufG(1'b1) 456 ) u_prim_clock_mux2 ( 457 .clk0_i(jtag_in_int.tck), 458 .clk1_i(clk_i), 459 .sel_i (testmode), 460 .clk_o (tck_muxed) 461 ); 462 463 prim_clock_mux2 #( 464 .NoFpgaBufG(1'b1) 465 ) u_prim_rst_n_mux2 ( 466 .clk0_i(jtag_in_int.trst_n), 467 .clk1_i(scan_rst_ni), 468 .sel_i (testmode), 469 .clk_o (trst_n_muxed) 470 ); 471 472 // JTAG TAP 473 dmi_jtag #( 474 .IdcodeValue (IdcodeValue), 475 .NumDmiWordAbits(7) 476 ) dap ( 477 .clk_i (clk_i), 478 .rst_ni (rst_ni), 479 .testmode_i (testmode), 480 .test_rst_ni (scan_rst_ni), 481 482 .dmi_rst_no (dmi_rst_n), 483 .dmi_req_o (dmi_req), 484 .dmi_req_valid_o (dmi_req_valid), 485 .dmi_req_ready_i (dmi_req_ready & dmi_en), 486 487 .dmi_resp_i (dmi_rsp ), 488 .dmi_resp_ready_o (dmi_rsp_ready), 489 .dmi_resp_valid_i (dmi_rsp_valid & dmi_en), 490 491 //JTAG 492 .tck_i (tck_muxed), 493 .tms_i (jtag_in_int.tms), 494 .trst_ni (trst_n_muxed), 495 .td_i (jtag_in_int.tdi), 496 .td_o (jtag_out_int.tdo), 497 .tdo_oe_o (jtag_out_int.tdo_oe) 498 ); 499 `endif 500 501 // SEC_CM: DM_EN.CTRL.LC_GATED 502 // SEC_CM: MEM_TL_LC_GATE.FSM.SPARSE 503 tlul_pkg::tl_h2d_t mem_tl_win_h2d_gated; 504 tlul_pkg::tl_d2h_t mem_tl_win_d2h_gated; 505 tlul_lc_gate #( 506 .NumGatesPerDirection(2) 507 ) u_tlul_lc_gate_rom ( 508 .clk_i, 509 .rst_ni, 510 .tl_h2d_i(mem_tl_win_h2d), 511 .tl_d2h_o(mem_tl_win_d2h), 512 .tl_h2d_o(mem_tl_win_h2d_gated), 513 .tl_d2h_i(mem_tl_win_d2h_gated), 514 .flush_req_i(ndmreset_req), 515 .flush_ack_o(ndmreset_req_qual), 516 .resp_pending_o(), 517 .lc_en_i (lc_hw_debug_en_gated[LcEnRom]), 518 .err_o (rom_gate_intg_error) 519 ); 520 521 prim_mubi_pkg::mubi4_t en_ifetch; 522 // SEC_CM: DM_EN.CTRL.LC_GATED, EXEC.CTRL.MUBI 523 1/1 assign en_ifetch = mubi4_bool_to_mubi(lc_tx_test_true_strict(lc_hw_debug_en_gated[LcEnFetch])); Tests: T1 T2 T3  524 525 tlul_adapter_reg #( 526 .CmdIntgCheck (1), 527 .EnableRspIntgGen (1), 528 .EnableDataIntgGen(1), 529 .RegAw (MemAw), 530 .RegDw (BusWidth), 531 .AccessLatency (1) 532 ) i_tlul_adapter_reg ( 533 .clk_i, 534 .rst_ni, 535 .tl_i (mem_tl_win_h2d_gated), 536 .tl_o (mem_tl_win_d2h_gated), 537 // SEC_CM: EXEC.CTRL.MUBI 538 .en_ifetch_i (en_ifetch), 539 // SEC_CM: BUS.INTEGRITY 540 .intg_error_o(rom_intg_error), 541 .re_o (device_re), 542 .we_o (device_we), 543 .addr_o (device_addr), 544 .wdata_o (device_wdata), 545 .be_o (device_be), 546 .busy_i (1'b0), 547 .rdata_i (device_rdata), 548 .error_i (device_err) 549 ); 550 551 1/1 assign device_req = device_we || device_re; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions423890.48
Logical423890.48
Non-Logical00
Event00

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTestsExclude Annotation
0000CoveredT1,T2,T3
0001ExcludedT43,T57 VC_COV_UNR
0010ExcludedT49,T53 VC_COV_UNR
0100Not Covered
1000CoveredT48,T87,T88

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT45,T46,T47
10CoveredT3,T6,T12
11CoveredT45,T46,T47

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T30,T25
11CoveredT1,T14,T44

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T14,T86
11CoveredT1,T14,T86

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T14,T86
10Excluded VC_COV_UNR
11CoveredT14,T30,T25

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------
-1--2-StatusTests
01CoveredT1,T6,T12
10CoveredT1,T14,T86
11CoveredT14,T30,T25

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------
-1--2-StatusTestsExclude Annotation
01CoveredT14,T30,T25
10Excluded VC_COV_UNR
11CoveredT14,T30,T25

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----
-1--2--3--4--5-StatusTestsExclude Annotation
01111Excluded VC_COV_UNR
10111CoveredT1,T44,T56
11011CoveredT14,T30,T25
11101CoveredT14,T30,T25
11110Not Covered
11111CoveredT14,T30,T25

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86,T89,T55
11CoveredT1,T3,T12

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T90,T43
11CoveredT1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T14,T42
10CoveredT3,T6,T12

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T90,T43
11CoveredT1,T2,T3

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 91 84 92.31
Total Bits 1082 1056 97.60
Total Bits 0->1 541 528 97.60
Total Bits 1->0 541 528 97.60

Ports 91 84 92.31
Port Bits 1082 1056 97.60
Port Bits 0->1 541 528 97.60
Port Bits 1->0 541 528 97.60

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_lc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T43,T44,T30 Yes T1,T2,T3 INPUT
rst_lc_ni Yes Yes T14,T43,T44 Yes T1,T2,T3 INPUT
next_dm_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
lc_hw_debug_en_i[3:0] Yes Yes T86,T25,T91 Yes T86,T25,T89 INPUT
lc_dft_en_i[3:0] No No No INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T7,T30,T25 Yes T7,T30,T25 INPUT
otp_dis_rv_dm_late_debug_i[7:0] Yes Yes T30,T92,T59 Yes T30,T92,T59 INPUT
scanmode_i[3:0] Yes Yes T44,T30,T25 Yes T30,T25,T92 INPUT
scan_rst_ni Yes Yes T43,T44,T30 Yes T1,T2,T3 INPUT
ndmreset_req_o Yes Yes T1,T14,T44 Yes T1,T14,T44 OUTPUT
dmactive_o Yes Yes T1,T8,T43 Yes T1,T2,T3 OUTPUT
debug_req_o Yes Yes T1,T28,T42 Yes T1,T3,T12 OUTPUT
unavailable_i Yes Yes T1,T5,T28 Yes T1,T4,T5 INPUT
regs_tl_d_i.d_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T3,T31,T7 Yes T6,T31,T7 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T31,T15,T43 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T6,T31,T42 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T3,T6,T42 Yes T3,T31,T42 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T3,T31,T7 Yes T31,T7,T42 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T3,T6,T31 Yes T3,T31,T7 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T3,T6,T7 Yes T31,T24,T29 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T3,T6,T31 Yes T3,T6,T31 INPUT
regs_tl_d_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_error Yes Yes T68,T50,T37 Yes T68,T50,T37 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] Yes Yes T68,T50,T37 Yes T68,T50,T37 OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T43,*T44,*T45 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_data[31:0] Yes Yes T43,T44,T30 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_sink Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_source[7:0] Yes Yes T45,T30,T25 Yes T12,T28,T14 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T45,T47,T93 Yes T45,T47,T93 OUTPUT
regs_tl_d_o.d_param[2:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
regs_tl_d_o.d_opcode[0] Yes Yes *T68,*T50,*T37 Yes T68,T50,T37 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_i.d_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T1,T6,T13 Yes T6,T31,T42 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T13,T28,T42 Yes T13,T42,T8 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T6,T13,T42 Yes T1,T6,T13 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T6,T13,T42 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T1,T6,T13 Yes T6,T13,T31 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T6,T13,T42 Yes T6,T42,T8 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T1,T6,T13 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T6,T13,T14 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T6,T13,T31 Yes T6,T13,T42 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T1,T6,T13 Yes T6,T13,T8 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T1,T6,T13 Yes T6,T13,T31 INPUT
mem_tl_d_i.a_valid Yes Yes T3,T6,T12 Yes T3,T6,T12 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T14,T41,T43 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T42,T69,T71 Yes T42,T69,T71 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T31,*T14,*T42 Yes T3,T6,T12 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T3,T6,T12 OUTPUT
mem_tl_d_o.d_sink Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_source[7:0] Yes Yes T14,T69,T71 Yes T3,T6,T13 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T31,T66,T30 Yes T12,T13,T31 OUTPUT
mem_tl_d_o.d_param[2:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T28,T14,T42 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T3,T6,T12 Yes T3,T6,T12 OUTPUT
sba_tl_h_o.d_ready Yes Yes T14,T43,T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T2,T14,T20 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T14,*T43,*T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T14,T43,T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_data[31:0] Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T2,T14,T20 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[1:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_address[31:2] Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_source[7:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_size[0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_size[1] Yes Yes T14,T43,T44 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_param[2:0] Excluded Excluded Excluded OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR
sba_tl_h_o.a_opcode[0] Yes Yes *T2,*T20,*T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T2,T14,T20 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_valid Yes Yes T2,T20,T21 Yes T2,T20,T21 OUTPUT
sba_tl_h_i.a_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T2,T20,T44 Yes T12,T29,T20 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T2,T12,T24 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T2,T24,T20 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T24,T20,T44 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_sink Yes Yes T29,T20,T44 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T24,T20,T44 Yes T29,T20,T44 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T24,T29,T20 Yes T20,T44,T94 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T12,T20,T44 Yes T20,T44,T94 INPUT
sba_tl_h_i.d_opcode[2:0] Yes Yes T2,T20,T44 Yes T2,T20,T44 INPUT
sba_tl_h_i.d_valid Yes Yes T2,T20,T21 Yes T2,T20,T21 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T45,T48 Yes T43,T45,T48 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T45,T48 Yes T43,T45,T48 OUTPUT
jtag_i.tdi Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.trst_n Yes Yes T7,T24,T43 Yes T1,T2,T3 INPUT
jtag_i.tms Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.tck Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_o.tdo_oe Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
jtag_o.tdo Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 320 7 7 100.00


320 if (!rst_ni) begin -1- 321 ndmreset_pending_q <= 1'b0; ==> 322 lc_rst_pending_q <= 1'b0; 323 end else begin 324 // Only set this if there was no previous pending NDM request. 325 if (ndmreset_req && !ndmreset_pending_q) begin -2- 326 ndmreset_pending_q <= 1'b1; ==> 327 end else if (ndmreset_ack && ndmreset_pending_q) begin -3- 328 ndmreset_pending_q <= 1'b0; ==> 329 end MISSING_ELSE ==> 330 // We only track lc resets that are asserted during an active ndm reset request.. 331 if (ndmreset_pending_q && lc_rst_asserted) begin -4- 332 lc_rst_pending_q <= 1'b1; ==> 333 end else if (ndmreset_ack && lc_rst_pending_q) begin -5- 334 lc_rst_pending_q <= 1'b0; ==> 335 end MISSING_ELSE ==>

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T14,T86
0 0 1 - - Covered T14,T30,T25
0 0 0 - - Covered T1,T2,T3
0 - - 1 - Covered T14,T30,T25
0 - - 0 1 Covered T14,T30,T25
0 - - 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 57068224 57005635 0 0
DmactiveOKnown_A 57068224 57005635 0 0
FpvSecCmRegWeOnehotCheck_A 57068224 80 0 0
FpvSecCmRomTlLcGateFsm_A 57068224 2 0 0
FpvSecCmSbaTlLcGateFsm_A 57068224 2 0 0
JtagRspOTdoKnown_A 2588102 2588034 0 0
JtagRspOTdoOeKnown_A 2588102 2588034 0 0
NdmresetOKnown_A 57068224 57005635 0 0
RvDmLcEnDebugVal_A 57068224 57005635 0 0
TlMemAReadyKnown_A 57068224 57005635 0 0
TlMemDValidKnown_A 57068224 57005635 0 0
TlRegsAReadyKnown_A 57068224 57005635 0 0
TlRegsDValidKnown_A 57068224 57005635 0 0
TlSbaAValidKnown_A 57068224 57005635 0 0
TlSbaDReadyKnown_A 57068224 57005635 0 0
paramCheckNrHarts 262 262 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 80 0 0
T21 200349 0 0 0
T25 34635 0 0 0
T32 39529 0 0 0
T48 27629 20 0 0
T54 61882 0 0 0
T58 12951 0 0 0
T60 13668 0 0 0
T67 3361 0 0 0
T72 2071 0 0 0
T83 7943 0 0 0
T87 0 10 0 0
T88 0 10 0 0
T95 0 20 0 0
T96 0 20 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 2 0 0
T16 6932 0 0 0
T30 19106 0 0 0
T43 5584 1 0 0
T44 207714 0 0 0
T45 4938 0 0 0
T48 27629 0 0 0
T57 0 1 0 0
T94 1448 0 0 0
T97 8078 0 0 0
T98 8099 0 0 0
T99 13727 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 2 0 0
T47 2172 0 0 0
T49 1228 1 0 0
T53 8609 1 0 0
T55 10855 0 0 0
T56 5620 0 0 0
T85 338350 0 0 0
T91 75768 0 0 0
T100 125319 0 0 0
T101 67288 0 0 0
T102 2301 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2588102 2588034 0 0
T1 3574 3574 0 0
T2 5567 5567 0 0
T3 842 842 0 0
T4 388 388 0 0
T5 1276 1276 0 0
T6 370 370 0 0
T12 578 578 0 0
T13 1329 1329 0 0
T28 769 769 0 0
T31 901 901 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2588102 2588034 0 0
T1 3574 3574 0 0
T2 5567 5567 0 0
T3 842 842 0 0
T4 388 388 0 0
T5 1276 1276 0 0
T6 370 370 0 0
T12 578 578 0 0
T13 1329 1329 0 0
T28 769 769 0 0
T31 901 901 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57068224 57005635 0 0
T1 50232 50169 0 0
T2 26875 26809 0 0
T3 2295 2245 0 0
T4 2303 2226 0 0
T5 10495 10427 0 0
T6 3474 3421 0 0
T12 17537 17473 0 0
T13 40613 40558 0 0
T28 30645 30591 0 0
T31 28098 28043 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T28 1 1 0 0
T31 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%