SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi32False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi32Width'(mubi_i); Tests: T1 T2 T3 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi32Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi32Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 4/4 assign mubi_o[j] = mubi32_t'(mubi_out); Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 262 | 262 | 0 | 0 |
OutputsKnown_A | 57068224 | 57005635 | 0 | 0 |
gen_no_flops.OutputDelay_A | 57068224 | 57005635 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 262 | 262 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57068224 | 57005635 | 0 | 0 |
T1 | 50232 | 50169 | 0 | 0 |
T2 | 26875 | 26809 | 0 | 0 |
T3 | 2295 | 2245 | 0 | 0 |
T4 | 2303 | 2226 | 0 | 0 |
T5 | 10495 | 10427 | 0 | 0 |
T6 | 3474 | 3421 | 0 | 0 |
T12 | 17537 | 17473 | 0 | 0 |
T13 | 40613 | 40558 | 0 | 0 |
T28 | 30645 | 30591 | 0 | 0 |
T31 | 28098 | 28043 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57068224 | 57005635 | 0 | 0 |
T1 | 50232 | 50169 | 0 | 0 |
T2 | 26875 | 26809 | 0 | 0 |
T3 | 2295 | 2245 | 0 | 0 |
T4 | 2303 | 2226 | 0 | 0 |
T5 | 10495 | 10427 | 0 | 0 |
T6 | 3474 | 3421 | 0 | 0 |
T12 | 17537 | 17473 | 0 | 0 |
T13 | 40613 | 40558 | 0 | 0 |
T28 | 30645 | 30591 | 0 | 0 |
T31 | 28098 | 28043 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |