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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
 dap 90.73 99.67 91.95 92.00 95.05 75.00
enable_checker 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
 i_tlul_adapter_reg 98.67 100.00 100.00 93.33 100.00 100.00
rv_dm_regs_csr_assert 100.00 100.00
 tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 100.00 100.00
tlul_assert_device_regs 98.25 98.25
tlul_assert_host_sba 97.18 97.18
 u_dm_top 87.45 90.31 73.26 92.86 80.84 100.00
 u_lc_en_sync_copies 100.00 100.00 100.00
 u_pm_en_sync 100.00 100.00 100.00 100.00
 u_prim_clock_mux2 100.00 100.00 100.00 100.00
 u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
 u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
 u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
 u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
 u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
 u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
 u_prim_rst_n_mux2 100.00 100.00 100.00 100.00
 u_reg_regs 98.58 100.00 99.35 93.55 100.00 100.00
 u_tlul_lc_gate_rom 97.78 100.00 100.00 100.00 100.00 88.89
 u_tlul_lc_gate_sba 90.81 94.49 84.00 100.00 86.67 88.89