Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32
1	1	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T96,T45,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7340543	7339055	0	0
selKnown1	53705041	53703553	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7340543	7339055	0	0
T1	1890	1888	0	0
T2	2832	2830	0	0
T3	9970	9968	0	0
T4	1746	1744	0	0
T5	648	646	0	0
T6	692	690	0	0
T7	4	2	0	0
T8	3	1	0	0
T12	1112	1110	0	0
T13	1876	1874	0	0
T14	2	0	0	0
T15	2	0	0	0
T17	1404	1402	0	0
T19	2	0	0	0
T20	0	18	0	0
T27	2	0	0	0
T38	1118	1116	0	0
T43	2	0	0	0
T54	2	0	0	0
T56	2	0	0	0
T69	0	2	0	0
T70	0	40	0	0
T74	0	1	0	0
T75	4	2	0	0
T76	0	2	0	0
T78	0	1	0	0
T96	0	1	0	0
T98	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	53705041	53703553	0	0
T1	6709	6707	0	0
T2	23075	23073	0	0
T3	70093	70091	0	0
T4	3563	3561	0	0
T5	2503	2501	0	0
T6	3233	3231	0	0
T12	11396	11394	0	0
T13	13597	13595	0	0
T17	5277	5275	0	0
T20	20	18	0	0
T21	0	16	0	0
T24	2	0	0	0
T38	5708	5706	0	0
T42	2	0	0	0
T46	2	0	0	0
T47	0	2	0	0
T48	2	0	0	0
T57	2	0	0	0
T69	4	2	0	0
T70	42	40	0	0
T74	0	2	0	0
T82	0	8	0	0
T84	0	2	0	0
T86	0	2	0	0
T89	0	40	0	0
T91	2	0	0	0
T96	2	0	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32
1	1	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T96,T45,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2205475	2205213	0	0
selKnown1	48570101	48569839	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2205475	2205213	0	0
T1	945	944	0	0
T2	1416	1415	0	0
T3	4985	4984	0	0
T4	873	872	0	0
T5	324	323	0	0
T6	346	345	0	0
T12	556	555	0	0
T13	938	937	0	0
T17	702	701	0	0
T38	559	558	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	48570101	48569839	0	0
T1	5764	5763	0	0
T2	21659	21658	0	0
T3	65108	65107	0	0
T4	2690	2689	0	0
T5	2179	2178	0	0
T6	2887	2886	0	0
T12	10840	10839	0	0
T13	12659	12658	0	0
T17	4575	4574	0	0
T38	5149	5148	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T177
1	1	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T96,T45,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	834	572	0	0
selKnown1	785	523	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	834	572	0	0
T7	2	1	0	0
T8	1	0	0	0
T14	1	0	0	0
T15	1	0	0	0
T19	1	0	0	0
T20	0	9	0	0
T21	0	8	0	0
T27	1	0	0	0
T43	1	0	0	0
T47	0	1	0	0
T54	1	0	0	0
T56	1	0	0	0
T69	0	1	0	0
T70	0	20	0	0
T74	0	1	0	0
T75	2	1	0	0
T76	0	1	0	0
T98	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	785	523	0	0
T20	10	9	0	0
T21	0	8	0	0
T24	1	0	0	0
T42	1	0	0	0
T46	1	0	0	0
T47	0	1	0	0
T48	1	0	0	0
T57	1	0	0	0
T69	2	1	0	0
T70	21	20	0	0
T74	0	1	0	0
T82	0	4	0	0
T84	0	1	0	0
T86	0	1	0	0
T89	0	20	0	0
T91	1	0	0	0
T96	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32
1	1	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T96,T45,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5132409	5131927	0	0
selKnown1	5132409	5131927	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5132409	5131927	0	0
T1	945	944	0	0
T2	1416	1415	0	0
T3	4985	4984	0	0
T4	873	872	0	0
T5	324	323	0	0
T6	346	345	0	0
T12	556	555	0	0
T13	938	937	0	0
T17	702	701	0	0
T38	559	558	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5132409	5131927	0	0
T1	945	944	0	0
T2	1416	1415	0	0
T3	4985	4984	0	0
T4	873	872	0	0
T5	324	323	0	0
T6	346	345	0	0
T12	556	555	0	0
T13	938	937	0	0
T17	702	701	0	0
T38	559	558	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T45,T177
1	1	Covered	T96,T45,T32

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T96,T45,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1825	1343	0	0
selKnown1	1746	1264	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1825	1343	0	0
T7	2	1	0	0
T8	2	1	0	0
T14	1	0	0	0
T15	1	0	0	0
T19	1	0	0	0
T20	0	9	0	0
T27	1	0	0	0
T43	1	0	0	0
T54	1	0	0	0
T56	1	0	0	0
T69	0	1	0	0
T70	0	20	0	0
T75	2	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T96	0	1	0	0
T98	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1746	1264	0	0
T20	10	9	0	0
T21	0	8	0	0
T24	1	0	0	0
T42	1	0	0	0
T46	1	0	0	0
T47	0	1	0	0
T48	1	0	0	0
T57	1	0	0	0
T69	2	1	0	0
T70	21	20	0	0
T74	0	1	0	0
T82	0	4	0	0
T84	0	1	0	0
T86	0	1	0	0
T89	0	20	0	0
T91	1	0	0	0
T96	1	0	0	0