Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	95.24	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	118629813	138901	0	0
late_debug_enable_rd_A	118629813	13817	0	0
late_debug_enable_regwen_rd_A	118629813	11876	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118629813	138901	0	0
T9	0	5785	0	0
T22	53787	0	0	0
T36	0	4259	0	0
T41	59135	1136	0	0
T49	0	9938	0	0
T51	5975	0	0	0
T65	0	3618	0	0
T79	166440	0	0	0
T83	0	5428	0	0
T109	0	6380	0	0
T114	0	7250	0	0
T116	0	7996	0	0
T123	0	3548	0	0
T124	164007	0	0	0
T125	22530	0	0	0
T126	11903	0	0	0
T127	418827	0	0	0
T128	1891	0	0	0
T129	88672	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118629813	13817	0	0
T9	0	2243	0	0
T22	53787	0	0	0
T41	59135	492	0	0
T51	5975	0	0	0
T65	0	1392	0	0
T79	166440	0	0	0
T109	0	1219	0	0
T114	0	1283	0	0
T124	164007	0	0	0
T125	22530	0	0	0
T126	11903	0	0	0
T127	418827	0	0	0
T128	1891	0	0	0
T129	88672	0	0	0
T137	0	2	0	0
T162	0	10	0	0
T174	0	86	0	0
T175	0	21	0	0
T176	0	13	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118629813	11876	0	0
T9	0	1587	0	0
T22	53787	0	0	0
T41	59135	436	0	0
T51	5975	0	0	0
T65	0	1091	0	0
T79	166440	0	0	0
T109	0	1331	0	0
T114	0	1107	0	0
T124	164007	0	0	0
T125	22530	0	0	0
T126	11903	0	0	0
T127	418827	0	0	0
T128	1891	0	0	0
T129	88672	0	0	0
T130	0	3	0	0
T137	0	8	0	0
T162	0	5	0	0
T174	0	16	0	0
T175	0	56	0	0