Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	965807	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1252339

1

T3

1

T11

1

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	672697	1			T42	3		T13	1		T47	10
values[0x0]	464295	1			T2	1		T3	1		T11	2
values[0x1]	1081154	1			T12	2		T5	1		T42	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	430741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1787405

1

T3

1

T11

1

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8371	1			T25	1		T55	144		T49	142
valid_sources[0x01]	8605	1			T195	1		T191	1		T55	116
valid_sources[0x02]	9077	1			T57	1		T58	1		T196	1
valid_sources[0x03]	8550	1			T191	1		T55	126		T49	180
valid_sources[0x04]	8554	1			T57	1		T58	1		T33	1
valid_sources[0x05]	8172	1			T55	131		T49	148		T65	209
valid_sources[0x06]	8440	1			T44	1		T55	114		T49	178
valid_sources[0x07]	8060	1			T57	1		T217	1		T55	124
valid_sources[0x08]	8590	1			T95	1		T39	2		T193	1
valid_sources[0x09]	8875	1			T12	3		T25	1		T55	143
valid_sources[0x0a]	8581	1			T57	1		T182	1		T188	1
valid_sources[0x0b]	7905	1			T16	1		T89	2		T55	143
valid_sources[0x0c]	8480	1			T217	1		T55	130		T49	170
valid_sources[0x0d]	8909	1			T58	2		T55	124		T49	167
valid_sources[0x0e]	8327	1			T55	151		T49	165		T65	247
valid_sources[0x0f]	8475	1			T200	1		T55	121		T49	160
valid_sources[0x10]	10056	1			T57	1		T55	133		T49	149
valid_sources[0x11]	8387	1			T58	1		T218	1		T55	155
valid_sources[0x12]	10406	1			T55	152		T49	163		T65	273
valid_sources[0x13]	8472	1			T55	171		T49	158		T65	232
valid_sources[0x14]	8525	1			T58	1		T55	133		T49	165
valid_sources[0x15]	8359	1			T217	1		T55	133		T49	164
valid_sources[0x16]	8910	1			T64	1		T55	156		T49	165
valid_sources[0x17]	8735	1			T55	126		T49	166		T65	264
valid_sources[0x18]	9002	1			T57	1		T55	147		T49	166
valid_sources[0x19]	8268	1			T48	1		T16	1		T199	7
valid_sources[0x1a]	8995	1			T187	12		T55	152		T49	176
valid_sources[0x1b]	10031	1			T58	1		T197	1		T55	121
valid_sources[0x1c]	8845	1			T181	2		T55	128		T49	178
valid_sources[0x1d]	8470	1			T55	139		T49	173		T65	249
valid_sources[0x1e]	8302	1			T57	1		T78	1		T55	143
valid_sources[0x1f]	8377	1			T219	1		T186	4		T55	163
valid_sources[0x20]	8729	1			T57	1		T15	3		T202	1
valid_sources[0x21]	9039	1			T53	1		T78	1		T182	1
valid_sources[0x22]	8673	1			T33	1		T55	130		T49	170
valid_sources[0x23]	8875	1			T44	1		T15	4		T182	3
valid_sources[0x24]	8399	1			T57	1		T190	1		T192	1
valid_sources[0x25]	8388	1			T13	1		T25	2		T55	156
valid_sources[0x26]	8460	1			T48	1		T29	4		T55	124
valid_sources[0x27]	9629	1			T219	1		T25	1		T10	1
valid_sources[0x28]	8261	1			T193	1		T55	140		T49	176
valid_sources[0x29]	8005	1			T182	1		T188	1		T200	1
valid_sources[0x2a]	9338	1			T185	10		T55	156		T49	150
valid_sources[0x2b]	8365	1			T192	1		T55	140		T49	172
valid_sources[0x2c]	8030	1			T55	126		T49	162		T65	294
valid_sources[0x2d]	8495	1			T196	1		T55	148		T49	154
valid_sources[0x2e]	8332	1			T57	6		T89	8		T25	1
valid_sources[0x2f]	8076	1			T51	1		T201	1		T192	1
valid_sources[0x30]	8253	1			T64	1		T78	1		T219	1
valid_sources[0x31]	8854	1			T48	1		T55	156		T49	157
valid_sources[0x32]	8333	1			T52	7		T193	1		T190	1
valid_sources[0x33]	8977	1			T55	141		T49	183		T65	247
valid_sources[0x34]	8426	1			T57	1		T58	4		T55	189
valid_sources[0x35]	9049	1			T58	2		T9	2		T189	13
valid_sources[0x36]	8255	1			T57	1		T78	1		T55	135
valid_sources[0x37]	8865	1			T184	14		T55	151		T49	153
valid_sources[0x38]	8684	1			T57	3		T64	2		T182	1
valid_sources[0x39]	8087	1			T51	1		T192	1		T55	114
valid_sources[0x3a]	9071	1			T201	2		T25	3		T29	2
valid_sources[0x3b]	8075	1			T58	1		T88	2		T10	2
valid_sources[0x3c]	9002	1			T55	104		T49	153		T65	274
valid_sources[0x3d]	9954	1			T30	3		T190	1		T55	145
valid_sources[0x3e]	8273	1			T35	1		T55	147		T49	169
valid_sources[0x3f]	9175	1			T55	126		T49	169		T65	293
valid_sources[0x40]	8547	1			T58	2		T55	127		T49	175
valid_sources[0x41]	8723	1			T182	1		T55	109		T49	182
valid_sources[0x42]	8302	1			T8	13		T25	1		T55	133
valid_sources[0x43]	8519	1			T58	2		T51	1		T193	2
valid_sources[0x44]	8649	1			T2	1		T89	3		T55	140
valid_sources[0x45]	8010	1			T57	2		T63	3		T55	139
valid_sources[0x46]	8972	1			T57	2		T78	1		T10	1
valid_sources[0x47]	8434	1			T9	1		T192	1		T55	157
valid_sources[0x48]	8552	1			T55	145		T49	177		T65	289
valid_sources[0x49]	9053	1			T58	3		T55	117		T49	189
valid_sources[0x4a]	8532	1			T58	3		T63	1		T193	1
valid_sources[0x4b]	8643	1			T57	1		T219	1		T55	156
valid_sources[0x4c]	8538	1			T55	131		T49	161		T65	259
valid_sources[0x4d]	8392	1			T17	2		T217	2		T183	26
valid_sources[0x4e]	8249	1			T90	2		T56	11		T31	8
valid_sources[0x4f]	8116	1			T89	1		T55	127		T49	152
valid_sources[0x50]	8542	1			T57	1		T64	2		T9	1
valid_sources[0x51]	8593	1			T58	1		T25	1		T55	134
valid_sources[0x52]	7718	1			T25	1		T55	151		T49	168
valid_sources[0x53]	8112	1			T51	1		T188	1		T25	1
valid_sources[0x54]	8659	1			T55	156		T49	161		T65	263
valid_sources[0x55]	9501	1			T78	1		T55	133		T49	180
valid_sources[0x56]	8607	1			T9	1		T55	137		T49	151
valid_sources[0x57]	8411	1			T55	123		T49	163		T65	230
valid_sources[0x58]	9013	1			T58	1		T35	3		T16	1
valid_sources[0x59]	8716	1			T16	1		T182	1		T191	3
valid_sources[0x5a]	8302	1			T47	11		T220	3		T55	153
valid_sources[0x5b]	8492	1			T55	137		T49	138		T65	279
valid_sources[0x5c]	8593	1			T44	1		T217	1		T190	2
valid_sources[0x5d]	9175	1			T55	143		T49	174		T65	264
valid_sources[0x5e]	8536	1			T89	2		T10	2		T55	133
valid_sources[0x5f]	8426	1			T182	1		T55	153		T49	172
valid_sources[0x60]	9134	1			T55	137		T49	141		T65	276
valid_sources[0x61]	9130	1			T51	1		T196	1		T9	1
valid_sources[0x62]	8517	1			T58	2		T55	158		T49	173
valid_sources[0x63]	8329	1			T57	2		T48	1		T78	1
valid_sources[0x64]	9649	1			T78	1		T55	124		T49	153
valid_sources[0x65]	8000	1			T55	132		T49	160		T65	310
valid_sources[0x66]	9093	1			T57	1		T55	95		T49	161
valid_sources[0x67]	8716	1			T55	178		T49	176		T65	259
valid_sources[0x68]	8505	1			T181	2		T55	145		T49	174
valid_sources[0x69]	8684	1			T57	1		T60	1		T55	114
valid_sources[0x6a]	8538	1			T25	1		T55	134		T49	184
valid_sources[0x6b]	9620	1			T58	1		T55	149		T49	158
valid_sources[0x6c]	8455	1			T188	2		T55	135		T49	168
valid_sources[0x6d]	9180	1			T57	2		T36	5		T55	134
valid_sources[0x6e]	8441	1			T57	1		T58	2		T54	1
valid_sources[0x6f]	8978	1			T58	1		T199	2		T25	1
valid_sources[0x70]	8384	1			T55	158		T49	172		T65	288
valid_sources[0x71]	9979	1			T58	2		T25	1		T55	156
valid_sources[0x72]	8432	1			T55	145		T49	133		T65	289
valid_sources[0x73]	9022	1			T192	1		T181	1		T55	142
valid_sources[0x74]	8094	1			T54	1		T55	152		T49	157
valid_sources[0x75]	8938	1			T57	1		T181	2		T55	139
valid_sources[0x76]	8951	1			T11	2		T57	2		T58	2
valid_sources[0x77]	8668	1			T58	1		T10	1		T186	5
valid_sources[0x78]	8792	1			T55	143		T49	172		T65	255
valid_sources[0x79]	8505	1			T57	1		T40	18		T55	150
valid_sources[0x7a]	8788	1			T57	1		T78	1		T55	125
valid_sources[0x7b]	8617	1			T5	1		T9	1		T55	165
valid_sources[0x7c]	8327	1			T54	1		T25	1		T203	1
valid_sources[0x7d]	8240	1			T25	1		T193	1		T192	1
valid_sources[0x7e]	8268	1			T203	1		T55	134		T49	169
valid_sources[0x7f]	8680	1			T57	1		T193	1		T55	142
valid_sources[0x80]	8660	1			T55	149		T49	167		T65	291

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

463888

1

T42

2

T13

1

T47

7

values[0x0]

all_enables

biggest_size

394905

1

T3

1

T11

1

T5

1

values[0x1]

all_enables

biggest_size

393546

1

T5

1

T43

1

T13

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1016189

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	272303	1			T55	7297		T49	7853		T65	12448
values[0x0]	384358	1			T1	1		T3	1		T11	1
values[0x1]	405006	1			T2	1		T18	1		T45	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23840	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1037827

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3419	1			T221	1		T34	3		T29	1
valid_sources[0x01]	3844	1			T55	112		T49	335		T65	274
valid_sources[0x02]	3795	1			T222	1		T163	1		T55	108
valid_sources[0x03]	3503	1			T223	1		T224	1		T55	120
valid_sources[0x04]	4384	1			T55	111		T49	34		T65	95
valid_sources[0x05]	3757	1			T184	1		T55	127		T49	33
valid_sources[0x06]	4381	1			T55	97		T49	179		T65	51
valid_sources[0x07]	4012	1			T225	1		T182	1		T29	1
valid_sources[0x08]	3492	1			T180	1		T55	97		T49	1
valid_sources[0x09]	4593	1			T226	1		T55	104		T49	148
valid_sources[0x0a]	3670	1			T227	9		T228	1		T55	122
valid_sources[0x0b]	4144	1			T142	2		T202	2		T55	120
valid_sources[0x0c]	3931	1			T229	1		T160	4		T230	1
valid_sources[0x0d]	4073	1			T231	5		T232	4		T55	92
valid_sources[0x0e]	3870	1			T55	101		T49	71		T65	17
valid_sources[0x0f]	4834	1			T233	1		T186	4		T66	1
valid_sources[0x10]	3961	1			T12	1		T233	2		T198	1
valid_sources[0x11]	4431	1			T47	1		T188	2		T203	1
valid_sources[0x12]	3618	1			T55	121		T49	348		T65	10
valid_sources[0x13]	3995	1			T234	6		T235	1		T224	1
valid_sources[0x14]	4736	1			T8	1		T236	9		T237	1
valid_sources[0x15]	4539	1			T93	1		T235	1		T221	1
valid_sources[0x16]	3838	1			T94	1		T199	7		T224	1
valid_sources[0x17]	5187	1			T157	1		T235	1		T187	1
valid_sources[0x18]	3977	1			T15	1		T230	1		T55	99
valid_sources[0x19]	4917	1			T238	1		T237	2		T55	90
valid_sources[0x1a]	3830	1			T141	2		T55	131		T49	197
valid_sources[0x1b]	4603	1			T143	1		T156	1		T239	1
valid_sources[0x1c]	4491	1			T162	1		T240	1		T55	116
valid_sources[0x1d]	5288	1			T55	130		T49	30		T65	375
valid_sources[0x1e]	3989	1			T241	2		T242	2		T226	2
valid_sources[0x1f]	4403	1			T202	1		T55	106		T49	114
valid_sources[0x20]	4085	1			T58	1		T243	2		T55	117
valid_sources[0x21]	3364	1			T244	1		T201	6		T224	1
valid_sources[0x22]	4005	1			T224	1		T238	1		T245	2
valid_sources[0x23]	5817	1			T55	125		T49	37		T65	8
valid_sources[0x24]	4247	1			T10	1		T55	115		T49	137
valid_sources[0x25]	4749	1			T55	135		T49	41		T65	431
valid_sources[0x26]	4316	1			T141	1		T55	115		T49	178
valid_sources[0x27]	4584	1			T113	1		T55	120		T49	184
valid_sources[0x28]	3542	1			T38	1		T242	3		T189	5
valid_sources[0x29]	4191	1			T41	2		T55	114		T49	36
valid_sources[0x2a]	4369	1			T237	1		T66	2		T55	118
valid_sources[0x2b]	4397	1			T246	3		T238	1		T247	1
valid_sources[0x2c]	4229	1			T142	2		T196	1		T224	1
valid_sources[0x2d]	4464	1			T1	1		T170	4		T248	2
valid_sources[0x2e]	4814	1			T62	1		T177	1		T66	1
valid_sources[0x2f]	4355	1			T55	106		T49	333		T65	124
valid_sources[0x30]	3817	1			T55	102		T49	236		T65	63
valid_sources[0x31]	4930	1			T224	1		T55	109		T49	255
valid_sources[0x32]	3484	1			T249	4		T229	1		T221	2
valid_sources[0x33]	3869	1			T55	129		T49	30		T65	155
valid_sources[0x34]	3532	1			T46	1		T96	1		T21	1
valid_sources[0x35]	4827	1			T250	1		T251	1		T55	116
valid_sources[0x36]	3412	1			T142	1		T55	125		T49	186
valid_sources[0x37]	4840	1			T60	1		T175	1		T238	1
valid_sources[0x38]	3370	1			T15	1		T226	1		T55	100
valid_sources[0x39]	3390	1			T55	124		T49	72		T65	211
valid_sources[0x3a]	4225	1			T11	1		T168	1		T55	116
valid_sources[0x3b]	3673	1			T15	1		T241	1		T242	1
valid_sources[0x3c]	4414	1			T53	1		T87	2		T182	1
valid_sources[0x3d]	4924	1			T252	1		T55	95		T49	122
valid_sources[0x3e]	3382	1			T29	1		T55	115		T49	94
valid_sources[0x3f]	3485	1			T171	1		T55	116		T49	41
valid_sources[0x40]	3322	1			T156	1		T253	1		T55	99
valid_sources[0x41]	4553	1			T246	1		T221	1		T190	1
valid_sources[0x42]	4767	1			T254	1		T255	1		T55	120
valid_sources[0x43]	4481	1			T17	1		T253	1		T203	1
valid_sources[0x44]	3641	1			T69	2		T52	1		T16	7
valid_sources[0x45]	3904	1			T239	2		T163	1		T256	1
valid_sources[0x46]	4087	1			T73	1		T252	2		T257	4
valid_sources[0x47]	4073	1			T258	1		T55	118		T49	129
valid_sources[0x48]	3707	1			T8	2		T55	95		T49	103
valid_sources[0x49]	4130	1			T248	1		T55	115		T49	7
valid_sources[0x4a]	3934	1			T259	1		T260	1		T55	98
valid_sources[0x4b]	4813	1			T88	1		T261	7		T55	108
valid_sources[0x4c]	4160	1			T29	1		T55	109		T49	159
valid_sources[0x4d]	4732	1			T260	2		T29	1		T55	109
valid_sources[0x4e]	3847	1			T224	1		T55	122		T49	158
valid_sources[0x4f]	3653	1			T21	1		T233	1		T254	1
valid_sources[0x50]	3586	1			T262	8		T240	1		T55	124
valid_sources[0x51]	3485	1			T55	108		T49	131		T65	212
valid_sources[0x52]	3422	1			T202	2		T241	1		T242	1
valid_sources[0x53]	4297	1			T44	1		T263	2		T33	1
valid_sources[0x54]	3406	1			T264	1		T221	3		T194	1
valid_sources[0x55]	3894	1			T40	8		T55	96		T49	286
valid_sources[0x56]	3729	1			T265	8		T188	1		T184	1
valid_sources[0x57]	3139	1			T153	1		T55	95		T49	71
valid_sources[0x58]	4201	1			T8	1		T232	1		T55	99
valid_sources[0x59]	5297	1			T229	3		T258	1		T159	1
valid_sources[0x5a]	3666	1			T266	2		T55	99		T49	37
valid_sources[0x5b]	4824	1			T55	109		T49	7		T65	230
valid_sources[0x5c]	2931	1			T4	1		T190	1		T55	115
valid_sources[0x5d]	3470	1			T163	1		T267	3		T182	2
valid_sources[0x5e]	3605	1			T2	1		T23	1		T50	1
valid_sources[0x5f]	5379	1			T268	3		T9	6		T248	4
valid_sources[0x60]	3532	1			T196	1		T55	89		T49	110
valid_sources[0x61]	4621	1			T42	1		T233	1		T196	1
valid_sources[0x62]	4038	1			T200	1		T203	1		T55	126
valid_sources[0x63]	3980	1			T269	1		T155	1		T240	1
valid_sources[0x64]	3490	1			T270	4		T55	99		T49	123
valid_sources[0x65]	3244	1			T45	1		T258	2		T200	1
valid_sources[0x66]	4958	1			T143	3		T202	1		T187	1
valid_sources[0x67]	4614	1			T55	116		T49	284		T65	137
valid_sources[0x68]	4007	1			T229	1		T8	1		T271	1
valid_sources[0x69]	4078	1			T272	1		T260	1		T193	9
valid_sources[0x6a]	4468	1			T31	8		T261	1		T25	9
valid_sources[0x6b]	3739	1			T57	1		T8	1		T237	3
valid_sources[0x6c]	4103	1			T163	1		T240	1		T55	106
valid_sources[0x6d]	4754	1			T163	1		T221	1		T55	119
valid_sources[0x6e]	4667	1			T75	1		T55	111		T49	282
valid_sources[0x6f]	2977	1			T273	14		T242	1		T186	2
valid_sources[0x70]	4704	1			T55	116		T49	294		T65	6
valid_sources[0x71]	3875	1			T142	2		T15	1		T78	1
valid_sources[0x72]	3672	1			T274	1		T220	1		T165	3
valid_sources[0x73]	4721	1			T229	2		T221	1		T203	1
valid_sources[0x74]	3961	1			T275	5		T55	114		T49	21
valid_sources[0x75]	5222	1			T78	1		T55	113		T49	193
valid_sources[0x76]	4195	1			T55	91		T49	145		T65	312
valid_sources[0x77]	4614	1			T198	1		T194	1		T55	96
valid_sources[0x78]	4304	1			T76	1		T229	2		T276	1
valid_sources[0x79]	5989	1			T173	1		T163	1		T55	101
valid_sources[0x7a]	5373	1			T163	2		T180	1		T55	98
valid_sources[0x7b]	3170	1			T97	1		T198	1		T194	1
valid_sources[0x7c]	3974	1			T114	1		T220	2		T277	1
valid_sources[0x7d]	3187	1			T142	1		T55	111		T49	264
valid_sources[0x7e]	3891	1			T192	10		T55	101		T49	1
valid_sources[0x7f]	4411	1			T41	2		T164	3		T278	1
valid_sources[0x80]	3697	1			T169	1		T235	1		T279	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

255169

1

T55

6902

T49

7403

T65

11743

values[0x0]

all_enables

biggest_size

380443

1

T1

1

T3

1

T11

1

values[0x1]

all_enables

biggest_size

380577

1

T2

1

T18

1

T45

1