Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	289665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

617862

1

T1

3

T3

1

T17

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	521230	1			T1	1		T17	2		T12	3
values[0x0]	160094	1			T1	1		T3	2		T12	3
values[0x1]	226203	1			T1	1		T3	1		T12	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

718945

1

T1

3

T3

1

T17

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3365	1			T50	1		T227	1		T62	34
valid_sources[0x01]	3709	1			T50	1		T62	30		T36	32
valid_sources[0x02]	4160	1			T47	1		T62	33		T36	30
valid_sources[0x03]	3217	1			T50	2		T62	27		T147	2
valid_sources[0x04]	4406	1			T62	42		T36	33		T34	17
valid_sources[0x05]	4066	1			T62	46		T36	13		T34	24
valid_sources[0x06]	3321	1			T50	1		T58	1		T62	29
valid_sources[0x07]	3099	1			T62	40		T36	35		T34	16
valid_sources[0x08]	2903	1			T50	1		T61	1		T62	50
valid_sources[0x09]	3908	1			T12	7		T50	1		T62	24
valid_sources[0x0a]	3381	1			T25	1		T62	40		T36	32
valid_sources[0x0b]	3291	1			T38	9		T62	24		T36	27
valid_sources[0x0c]	3401	1			T46	1		T227	1		T62	41
valid_sources[0x0d]	2790	1			T47	1		T57	1		T62	27
valid_sources[0x0e]	3187	1			T55	1		T15	1		T62	30
valid_sources[0x0f]	3487	1			T9	1		T69	1		T62	27
valid_sources[0x10]	3254	1			T62	34		T36	28		T34	21
valid_sources[0x11]	3623	1			T46	1		T61	1		T70	1
valid_sources[0x12]	3345	1			T50	1		T62	33		T36	32
valid_sources[0x13]	3521	1			T50	1		T62	39		T36	30
valid_sources[0x14]	3756	1			T10	2		T25	1		T62	29
valid_sources[0x15]	3630	1			T62	45		T36	36		T34	17
valid_sources[0x16]	3018	1			T62	26		T36	33		T34	9
valid_sources[0x17]	3458	1			T62	31		T36	33		T34	11
valid_sources[0x18]	3132	1			T47	1		T62	25		T36	28
valid_sources[0x19]	3611	1			T9	1		T69	4		T62	39
valid_sources[0x1a]	3781	1			T64	17		T227	2		T62	33
valid_sources[0x1b]	2984	1			T50	1		T70	2		T62	34
valid_sources[0x1c]	3312	1			T62	42		T36	28		T34	18
valid_sources[0x1d]	4200	1			T62	32		T36	30		T34	12
valid_sources[0x1e]	3143	1			T62	34		T36	28		T34	5
valid_sources[0x1f]	3584	1			T64	22		T45	1		T229	2
valid_sources[0x20]	3207	1			T62	37		T39	1		T36	32
valid_sources[0x21]	3544	1			T62	29		T36	30		T34	13
valid_sources[0x22]	3839	1			T50	1		T68	1		T62	37
valid_sources[0x23]	3666	1			T62	31		T39	1		T36	33
valid_sources[0x24]	3249	1			T47	1		T62	37		T36	32
valid_sources[0x25]	2967	1			T64	5		T58	3		T62	17
valid_sources[0x26]	3443	1			T62	28		T36	20		T34	11
valid_sources[0x27]	3445	1			T62	28		T36	36		T34	11
valid_sources[0x28]	3179	1			T50	1		T61	1		T62	23
valid_sources[0x29]	2919	1			T25	1		T62	27		T36	27
valid_sources[0x2a]	3573	1			T44	1		T59	1		T62	39
valid_sources[0x2b]	3146	1			T50	2		T62	32		T36	40
valid_sources[0x2c]	4053	1			T62	38		T36	31		T34	12
valid_sources[0x2d]	2820	1			T62	38		T36	33		T34	11
valid_sources[0x2e]	3589	1			T9	1		T62	34		T36	37
valid_sources[0x2f]	2864	1			T60	2		T69	1		T73	2
valid_sources[0x30]	3307	1			T230	1		T62	28		T36	36
valid_sources[0x31]	3466	1			T50	1		T70	1		T25	1
valid_sources[0x32]	2912	1			T62	30		T36	23		T34	18
valid_sources[0x33]	3650	1			T62	36		T36	29		T34	11
valid_sources[0x34]	3323	1			T62	44		T36	39		T34	9
valid_sources[0x35]	4221	1			T50	1		T62	33		T36	32
valid_sources[0x36]	3217	1			T50	1		T27	3		T44	3
valid_sources[0x37]	4591	1			T60	2		T62	29		T36	30
valid_sources[0x38]	3607	1			T62	45		T36	25		T34	25
valid_sources[0x39]	3566	1			T31	1		T62	36		T36	32
valid_sources[0x3a]	3507	1			T62	40		T152	4		T39	1
valid_sources[0x3b]	3540	1			T44	1		T62	35		T39	1
valid_sources[0x3c]	3599	1			T50	1		T65	1		T62	27
valid_sources[0x3d]	3867	1			T69	1		T68	1		T62	24
valid_sources[0x3e]	4308	1			T50	1		T61	1		T44	1
valid_sources[0x3f]	3044	1			T25	1		T62	29		T36	30
valid_sources[0x40]	3688	1			T50	1		T56	1		T62	35
valid_sources[0x41]	3337	1			T47	1		T62	31		T36	27
valid_sources[0x42]	3733	1			T62	27		T36	22		T34	8
valid_sources[0x43]	3414	1			T3	3		T68	1		T62	28
valid_sources[0x44]	3517	1			T50	1		T62	38		T36	31
valid_sources[0x45]	3591	1			T50	1		T62	32		T36	32
valid_sources[0x46]	3337	1			T229	1		T62	32		T36	39
valid_sources[0x47]	3536	1			T62	34		T36	41		T34	14
valid_sources[0x48]	3258	1			T24	1		T62	47		T36	23
valid_sources[0x49]	3018	1			T62	30		T36	37		T34	9
valid_sources[0x4a]	3469	1			T62	27		T36	31		T34	14
valid_sources[0x4b]	10153	1			T50	2		T62	35		T36	22
valid_sources[0x4c]	4337	1			T62	41		T39	1		T36	27
valid_sources[0x4d]	3028	1			T62	46		T36	26		T34	17
valid_sources[0x4e]	2912	1			T62	40		T36	28		T34	14
valid_sources[0x4f]	3581	1			T62	41		T36	32		T34	22
valid_sources[0x50]	3393	1			T9	1		T44	1		T62	41
valid_sources[0x51]	4178	1			T59	1		T227	2		T62	27
valid_sources[0x52]	4382	1			T11	4		T62	23		T36	31
valid_sources[0x53]	2960	1			T68	1		T62	36		T36	32
valid_sources[0x54]	2930	1			T62	29		T223	2		T36	33
valid_sources[0x55]	3714	1			T64	3		T62	25		T36	18
valid_sources[0x56]	3271	1			T62	20		T36	28		T34	15
valid_sources[0x57]	3360	1			T62	41		T36	36		T34	12
valid_sources[0x58]	3371	1			T70	1		T62	43		T36	35
valid_sources[0x59]	2885	1			T62	27		T36	24		T34	15
valid_sources[0x5a]	3427	1			T41	1		T62	34		T36	28
valid_sources[0x5b]	3335	1			T58	4		T62	28		T36	33
valid_sources[0x5c]	3844	1			T62	38		T36	30		T34	18
valid_sources[0x5d]	2789	1			T62	22		T36	25		T34	14
valid_sources[0x5e]	3446	1			T33	1		T25	1		T62	36
valid_sources[0x5f]	3369	1			T10	1		T62	42		T36	29
valid_sources[0x60]	3026	1			T50	1		T66	1		T62	20
valid_sources[0x61]	3358	1			T43	1		T62	22		T36	19
valid_sources[0x62]	3005	1			T62	28		T36	25		T34	23
valid_sources[0x63]	3952	1			T17	2		T70	1		T25	1
valid_sources[0x64]	3225	1			T50	2		T62	22		T36	29
valid_sources[0x65]	3946	1			T29	1		T62	26		T36	29
valid_sources[0x66]	3437	1			T50	1		T9	1		T25	1
valid_sources[0x67]	3452	1			T33	1		T62	24		T36	28
valid_sources[0x68]	3851	1			T61	1		T25	1		T62	35
valid_sources[0x69]	3483	1			T62	47		T36	24		T34	7
valid_sources[0x6a]	4123	1			T59	1		T62	36		T36	36
valid_sources[0x6b]	3119	1			T50	1		T62	37		T36	39
valid_sources[0x6c]	3696	1			T50	1		T62	25		T36	24
valid_sources[0x6d]	3930	1			T50	3		T57	1		T24	1
valid_sources[0x6e]	3409	1			T47	1		T62	29		T36	41
valid_sources[0x6f]	3790	1			T30	1		T57	1		T11	4
valid_sources[0x70]	4020	1			T57	1		T62	40		T36	29
valid_sources[0x71]	3299	1			T62	36		T36	32		T34	6
valid_sources[0x72]	3572	1			T222	2		T62	32		T36	44
valid_sources[0x73]	3939	1			T46	1		T62	20		T36	37
valid_sources[0x74]	4125	1			T62	30		T36	27		T34	21
valid_sources[0x75]	3182	1			T50	1		T62	22		T36	29
valid_sources[0x76]	3088	1			T50	2		T44	3		T128	1
valid_sources[0x77]	3170	1			T62	28		T39	1		T36	26
valid_sources[0x78]	3099	1			T62	29		T36	28		T34	14
valid_sources[0x79]	3353	1			T15	1		T62	23		T36	26
valid_sources[0x7a]	3332	1			T62	34		T36	29		T34	14
valid_sources[0x7b]	3441	1			T60	2		T59	1		T62	44
valid_sources[0x7c]	3256	1			T46	1		T62	29		T36	28
valid_sources[0x7d]	4046	1			T24	1		T62	24		T36	31
valid_sources[0x7e]	3406	1			T50	1		T68	1		T62	33
valid_sources[0x7f]	3023	1			T62	35		T36	33		T34	19
valid_sources[0x80]	3375	1			T10	1		T62	42		T36	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

314852

1

T1

1

T17

2

T12

3

values[0x0]

all_enables

biggest_size

151865

1

T1

1

T46

1

T114

1

values[0x1]

all_enables

biggest_size

151145

1

T1

1

T3

1

T4

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125626

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37119	1			T80	1		T90	1		T62	1335
values[0x0]	47462	1			T2	1		T48	13		T6	1
values[0x1]	50172	1			T1	1		T3	1		T17	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

129075

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	360	1			T247	1		T62	13		T146	1
valid_sources[0x01]	625	1			T182	1		T62	1		T149	3
valid_sources[0x02]	441	1			T40	1		T38	1		T248	1
valid_sources[0x03]	665	1			T249	1		T62	40		T36	29
valid_sources[0x04]	481	1			T51	1		T30	1		T62	20
valid_sources[0x05]	398	1			T250	6		T62	31		T185	1
valid_sources[0x06]	374	1			T251	2		T62	38		T36	11
valid_sources[0x07]	428	1			T62	5		T36	20		T34	4
valid_sources[0x08]	449	1			T252	1		T73	1		T251	1
valid_sources[0x09]	387	1			T132	2		T62	27		T36	13
valid_sources[0x0a]	546	1			T253	1		T62	13		T36	19
valid_sources[0x0b]	320	1			T254	2		T62	5		T36	11
valid_sources[0x0c]	503	1			T54	1		T62	12		T150	1
valid_sources[0x0d]	479	1			T255	1		T62	32		T36	23
valid_sources[0x0e]	634	1			T82	1		T113	1		T62	31
valid_sources[0x0f]	371	1			T125	1		T22	1		T248	1
valid_sources[0x10]	378	1			T111	1		T70	1		T57	1
valid_sources[0x11]	372	1			T62	27		T145	1		T152	1
valid_sources[0x12]	322	1			T230	1		T62	7		T36	15
valid_sources[0x13]	505	1			T131	1		T251	1		T62	27
valid_sources[0x14]	526	1			T4	1		T120	1		T62	11
valid_sources[0x15]	609	1			T62	7		T36	17		T34	12
valid_sources[0x16]	506	1			T58	1		T62	6		T36	24
valid_sources[0x17]	584	1			T58	1		T256	2		T62	31
valid_sources[0x18]	531	1			T57	1		T103	7		T62	37
valid_sources[0x19]	621	1			T107	1		T25	1		T62	11
valid_sources[0x1a]	492	1			T119	1		T202	1		T62	53
valid_sources[0x1b]	397	1			T257	3		T254	1		T62	14
valid_sources[0x1c]	416	1			T254	1		T68	1		T216	1
valid_sources[0x1d]	337	1			T84	1		T15	6		T24	9
valid_sources[0x1e]	416	1			T249	1		T62	14		T150	2
valid_sources[0x1f]	456	1			T62	3		T36	31		T34	8
valid_sources[0x20]	443	1			T216	1		T62	6		T36	7
valid_sources[0x21]	610	1			T257	2		T258	2		T62	32
valid_sources[0x22]	514	1			T83	1		T106	6		T62	15
valid_sources[0x23]	682	1			T259	1		T260	1		T62	16
valid_sources[0x24]	656	1			T208	1		T254	2		T62	39
valid_sources[0x25]	778	1			T62	35		T36	17		T34	4
valid_sources[0x26]	496	1			T261	2		T259	1		T62	32
valid_sources[0x27]	461	1			T62	9		T36	25		T34	7
valid_sources[0x28]	739	1			T68	1		T62	31		T36	20
valid_sources[0x29]	468	1			T262	1		T213	1		T62	28
valid_sources[0x2a]	579	1			T62	16		T36	23		T34	9
valid_sources[0x2b]	912	1			T62	49		T36	16		T34	8
valid_sources[0x2c]	517	1			T205	3		T230	2		T62	5
valid_sources[0x2d]	598	1			T182	1		T254	1		T59	1
valid_sources[0x2e]	539	1			T21	9		T62	7		T263	3
valid_sources[0x2f]	510	1			T46	1		T11	1		T62	19
valid_sources[0x30]	686	1			T251	2		T62	28		T36	19
valid_sources[0x31]	378	1			T80	3		T230	3		T62	13
valid_sources[0x32]	638	1			T153	1		T218	1		T255	1
valid_sources[0x33]	453	1			T254	1		T264	1		T62	37
valid_sources[0x34]	441	1			T38	1		T62	20		T150	1
valid_sources[0x35]	448	1			T251	2		T62	10		T265	4
valid_sources[0x36]	421	1			T62	14		T150	1		T36	18
valid_sources[0x37]	383	1			T62	19		T36	23		T34	6
valid_sources[0x38]	610	1			T62	52		T36	15		T34	9
valid_sources[0x39]	448	1			T51	1		T222	1		T266	1
valid_sources[0x3a]	553	1			T119	5		T62	6		T36	23
valid_sources[0x3b]	396	1			T267	1		T62	39		T36	22
valid_sources[0x3c]	415	1			T62	36		T39	2		T36	12
valid_sources[0x3d]	829	1			T268	5		T62	31		T36	25
valid_sources[0x3e]	436	1			T42	1		T269	1		T259	1
valid_sources[0x3f]	515	1			T2	1		T211	1		T270	1
valid_sources[0x40]	687	1			T122	1		T252	1		T271	1
valid_sources[0x41]	685	1			T54	1		T40	1		T72	1
valid_sources[0x42]	539	1			T272	1		T253	3		T62	18
valid_sources[0x43]	461	1			T248	1		T62	15		T36	28
valid_sources[0x44]	407	1			T40	1		T127	1		T129	1
valid_sources[0x45]	430	1			T184	1		T57	2		T59	1
valid_sources[0x46]	439	1			T11	1		T253	1		T62	15
valid_sources[0x47]	466	1			T74	1		T62	29		T36	18
valid_sources[0x48]	614	1			T7	1		T62	24		T36	18
valid_sources[0x49]	335	1			T123	1		T38	1		T62	14
valid_sources[0x4a]	689	1			T68	1		T62	34		T36	15
valid_sources[0x4b]	631	1			T131	1		T248	1		T62	32
valid_sources[0x4c]	423	1			T56	1		T115	7		T248	1
valid_sources[0x4d]	481	1			T273	1		T62	24		T36	10
valid_sources[0x4e]	439	1			T257	4		T274	1		T62	13
valid_sources[0x4f]	633	1			T86	2		T62	34		T150	1
valid_sources[0x50]	766	1			T69	1		T129	2		T254	2
valid_sources[0x51]	616	1			T229	1		T62	7		T36	10
valid_sources[0x52]	335	1			T248	1		T62	37		T39	2
valid_sources[0x53]	653	1			T253	1		T62	37		T36	21
valid_sources[0x54]	692	1			T257	3		T213	1		T62	30
valid_sources[0x55]	423	1			T11	1		T275	1		T62	16
valid_sources[0x56]	583	1			T62	10		T150	1		T36	24
valid_sources[0x57]	520	1			T62	12		T36	17		T34	6
valid_sources[0x58]	458	1			T182	1		T276	1		T255	2
valid_sources[0x59]	414	1			T277	1		T62	32		T36	21
valid_sources[0x5a]	524	1			T182	2		T229	1		T62	51
valid_sources[0x5b]	471	1			T105	1		T59	1		T62	6
valid_sources[0x5c]	347	1			T62	28		T148	1		T36	23
valid_sources[0x5d]	371	1			T276	3		T207	1		T254	2
valid_sources[0x5e]	404	1			T48	16		T5	1		T61	1
valid_sources[0x5f]	421	1			T130	6		T62	34		T36	19
valid_sources[0x60]	632	1			T62	15		T204	4		T36	12
valid_sources[0x61]	363	1			T62	32		T36	31		T34	10
valid_sources[0x62]	468	1			T62	12		T36	15		T34	7
valid_sources[0x63]	477	1			T62	37		T36	22		T34	9
valid_sources[0x64]	357	1			T38	1		T278	8		T62	18
valid_sources[0x65]	586	1			T62	45		T36	25		T34	10
valid_sources[0x66]	575	1			T62	19		T36	18		T34	17
valid_sources[0x67]	372	1			T76	1		T248	1		T62	57
valid_sources[0x68]	384	1			T64	1		T54	1		T22	1
valid_sources[0x69]	543	1			T257	1		T62	27		T36	26
valid_sources[0x6a]	724	1			T58	1		T62	37		T36	4
valid_sources[0x6b]	430	1			T43	1		T254	1		T62	24
valid_sources[0x6c]	505	1			T279	1		T62	26		T36	11
valid_sources[0x6d]	654	1			T102	1		T54	1		T119	1
valid_sources[0x6e]	718	1			T54	1		T248	1		T251	1
valid_sources[0x6f]	387	1			T12	1		T54	1		T255	1
valid_sources[0x70]	468	1			T248	1		T62	28		T185	1
valid_sources[0x71]	486	1			T3	1		T62	13		T36	13
valid_sources[0x72]	673	1			T23	1		T280	10		T68	1
valid_sources[0x73]	362	1			T60	1		T119	5		T257	1
valid_sources[0x74]	717	1			T248	1		T62	9		T36	23
valid_sources[0x75]	373	1			T217	1		T62	17		T36	19
valid_sources[0x76]	524	1			T22	1		T212	1		T271	2
valid_sources[0x77]	530	1			T229	1		T203	2		T62	23
valid_sources[0x78]	611	1			T67	1		T22	1		T252	1
valid_sources[0x79]	379	1			T17	1		T62	15		T36	14
valid_sources[0x7a]	500	1			T281	12		T255	1		T62	40
valid_sources[0x7b]	998	1			T62	32		T36	24		T34	11
valid_sources[0x7c]	590	1			T38	1		T257	1		T62	16
valid_sources[0x7d]	950	1			T62	28		T147	2		T36	13
valid_sources[0x7e]	398	1			T41	1		T38	1		T59	1
valid_sources[0x7f]	838	1			T249	1		T62	17		T36	9
valid_sources[0x80]	461	1			T128	1		T62	8		T36	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

32756

1

T62

1253

T36

1254

T34

540

values[0x0]

all_enables

biggest_size

46453

1

T2

1

T48

5

T6

1

values[0x1]

all_enables

biggest_size

46417

1

T1

1

T3

1

T17

1