Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

816956

1

T3

2

T12

4

T28

3

full_word

636614

1

T1

3

T3

1

T12

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1453254	1			T1	3		T3	3		T12	7
auto[TlIntgErrCmd]	110	1			T90	1		T24	1		T185	1
auto[TlIntgErrData]	95	1			T186	1		T198	4		T235	2
auto[TlIntgErrBoth]	111	1			T103	1		T198	9		T235	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

544648

1

T1

1

T12

3

T50

80

auto[1]

908922

1

T1

2

T3

3

T12

4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	227419	1			T47	3		T60	3		T46	1
auto[TlIntgErrNone]	partial	auto[1]	589250	1			T3	2		T12	4		T28	3
auto[TlIntgErrNone]	full_word	auto[0]	317084	1			T1	1		T12	3		T50	80
auto[TlIntgErrNone]	full_word	auto[1]	319501	1			T1	2		T3	1		T4	1
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T24	1		T185	1		T233	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T198	2		T188	3		T238	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T90	1		T236	1		T243	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T240	1		T236	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1			T198	2		T188	3		T238	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T186	1		T198	1		T235	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T238	1		T241	1		T244	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T198	1		T235	1		T241	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T103	1		T198	4		T188	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T198	4		T235	5		T188	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T198	1		T188	1		T238	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T188	1		T245	1		T246	1