Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5760318

1

T2

1

T11

1

T12

3

full_word

1416869

1

T3

1

T11

1

T5

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7176847	1			T2	1		T3	1		T11	2
auto[TlIntgErrCmd]	122	1			T145	9		T151	5		T152	6
auto[TlIntgErrData]	120	1			T145	6		T151	10		T152	11
auto[TlIntgErrBoth]	98	1			T145	5		T151	5		T152	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

871930

1

T42

3

T13

1

T47

10

auto[1]

6305257

1

T2

1

T3

1

T11

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	387781	1			T42	1		T47	3		T53	4
auto[TlIntgErrNone]	partial	auto[1]	5372226	1			T2	1		T11	1		T12	3
auto[TlIntgErrNone]	full_word	auto[0]	484002	1			T42	2		T13	1		T47	7
auto[TlIntgErrNone]	full_word	auto[1]	932838	1			T3	1		T11	1		T5	2
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T145	2		T151	2		T152	3
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T145	7		T151	2		T152	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T207	1		T211	1		T212	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T151	1		T213	2		T214	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T145	4		T151	5		T152	10
auto[TlIntgErrData]	partial	auto[1]	47	1			T145	2		T151	3		T152	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T151	1		T207	1		T208	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T151	1		T206	1		T209	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T145	1		T151	3		T152	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T145	4		T151	2		T152	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T152	1		T210	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T207	1		T211	1		-	-