Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_rv_dm_regs_reg_block.late_debug_enable.late_debug_enable	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_rv_dm_regs_reg_block.late_debug_enable.late_debug_enable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rv_dm_regs_reg_block.late_debug_enable.late_debug_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rv_dm_regs_reg_block.late_debug_enable.late_debug_enable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

374

1

T198

5

T158

2

T235

4

auto[1]

1031

1

T133

1

T136

2

T139

2