RV_TIMER Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	52.045m	130.332ms	193	200	96.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.580s	72.969us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	25.072us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.940s	90.326us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.790s	40.079us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.470s	34.713us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	25.072us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	40.079us	5	5	100.00
V1		TOTAL			248	255	97.25
V2	random_reset	rv_timer_random_reset	49.538m	162.285ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.408m	200.438ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	21.019m	3.043s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	21.019m	3.043s	50	50	100.00
V2	stress	rv_timer_stress_all	1.114h	2.204s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.640s	15.397us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.640s	53.952us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.640s	53.952us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.580s	72.969us	5	5	100.00
		rv_timer_csr_rw	0.610s	25.072us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	40.079us	5	5	100.00
		rv_timer_same_csr_outstanding	0.810s	55.160us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.580s	72.969us	5	5	100.00
		rv_timer_csr_rw	0.610s	25.072us	20	20	100.00
		rv_timer_csr_aliasing	0.790s	40.079us	5	5	100.00
		rv_timer_same_csr_outstanding	0.810s	55.160us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	0.970s	169.294us	5	5	100.00
		rv_timer_tl_intg_err	1.410s	215.375us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.410s	215.375us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	34.259m	221.157ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			612	620	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.38	98.73	100.00	--	100.00	100.00	99.77

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:

Test rv_timer_disabled has 1 failures.

3.rv_timer_disabled.3887887089
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_random has 6 failures.

90.rv_timer_random.730072938
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/90.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

99.rv_timer_random.245426521
Line 220, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/99.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 128.rv_timer_random.3022030983
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/128.rv_timer_random/latest/run.log
```
  Job ID: smart:6c377fd3-87d1-433a-b569-4371d2c79601
```